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1. 发明公开

EP1599894A4 METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS 审中-公开
标题翻译：法改善双掺杂的栅申请的轮廓控制和N / P LOAD的
公开(公告)号：EP1599894A4
公开(公告)日：2010-04-28
申请号：EP04715154
申请日：2004-02-26
申请人： LAM RES CORP
发明人： DEL PUPPO HELENE , LIN FRANK , LEE CHRIS , VAHEDI VAHID , KAMP THOMAS A , MILLER ALAN J
IPC分类号： H01L21/3213 , H01L21/302
CPC分类号： H01L21/32137

2. 发明申请

WO0175967B1 IN SITU AND EX SITU ETCHING PROCESS FOR STI WITH OXIDE COLLAR APPLICATION 审中-公开
标题翻译：氧化铬应用SITU原位和STI刻蚀工艺
公开(公告)号：WO0175967B1
公开(公告)日：2001-11-29
申请号：PCT/US0109564
申请日：2001-03-22
申请人： LAM RES CORP , MILLER ALAN J , SOESILO FANDAYANI
发明人： MILLER ALAN J , SOESILO FANDAYANI
IPC分类号： H01L21/3065 , H01L21/306 , H01L21/308 , H01L21/32 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L21/30604 , H01L21/308 , H01L21/32 , H01L21/76229 , H01L21/76232
摘要： A method or process for etching a trench in an IC structure is disclosed. The IC structure might be comprised of a plurality of different component materials arranged proximate to one another, all of which need to be etched down to a target level. A first etching chemistry is applied which preferentially etches a one type of component material. A second etching chemistry is applied which preferentially etches another type of component material. The method or process toggles back and forth between the etching chemistries until the target level is reached. The toggling techniques serves to maintain the profiles of the different component materials. One component material might also be embedded, as a collar or otherwise, around another component material. The toggling technique can serve to modulate the height, level, or shape of one material relative to another material. The toggling steps can be performed in situ or ex situ. The toggling technique can be used with different mask materials, including a photoresist or a hardmask over the IC structure.
摘要翻译：公开了一种蚀刻IC结构中的沟槽的方法或工艺。 IC结构可以由多个彼此接近布置的不同组件材料组成，所有这些材料都需要被蚀刻到目标水平。施加第一蚀刻化学品，其优先蚀刻一种类型的组分材料。施加第二蚀刻化学品，其优先蚀刻另一种类型的组分材料。该方法或过程在蚀刻化学物质之间来回切换，直至达到目标水平。切换技术用于维护不同组件材料的轮廓。一种组件材料也可以嵌入另一种组件材料中作为颈圈或其他材料。切换技术可用于调节一种材料相对于另一种材料的高度，高度或形状。切换步骤可以原位或异地进行。切换技术可以用于不同的掩模材料，包括IC结构上的光刻胶或硬掩模。

3. 发明申请

WO2004030050A2 APPARATUS AND METHOD FOR CONTROLLING ETCH DEPTH 审中-公开
标题翻译：用于控制蚀刻深度的装置和方法
公开(公告)号：WO2004030050A2
公开(公告)日：2004-04-08
申请号：PCT/US0330117
申请日：2003-09-18
申请人： LAM RES CORP , KAMP TOM A , MILLER ALAN J , VENUGOPAL VIJAYAKUMAR C
发明人： KAMP TOM A , MILLER ALAN J , VENUGOPAL VIJAYAKUMAR C
IPC分类号： H01L21/00 , H01L21/3065
CPC分类号： H01L21/67253 , H01J37/321 , H01J37/32963 , H01L21/3065 , H01L21/67069
摘要： An apparatus and method for etching a feature in a wafer with improved depth control and reproducibility is described. The feature is etched at a first etching rate and then at a second etching rate, which is slower than the first etching rate. An optical end point device is used to determine the etching depth and etching is stopped so that the feature has the desired depth. Two different etching rates provides high throughput with good depth control and reproducibility. The apparatus includes an etching tool in which a chuck holds the wafer to be etched. An optical end point device is positioned to measure the feature etch depth. An electronic controller communicates with the optical end point device and the etching tool to control the tool to reduce the etch rate part way through etching the feature and to stop the etching tool, so that that the feature is etched to the desired depth.
摘要翻译：描述了用改进的深度控制和再现性来蚀刻晶片中的特征的设备和方法。该特征以第一蚀刻速率蚀刻，然后以比第一蚀刻速率慢的第二蚀刻速率蚀刻。使用光学终点设备来确定蚀刻深度并且停止蚀刻，使得该特征具有期望的深度。两种不同的蚀刻速率提供了高通量和良好的深度控制和可重复性。该设备包括蚀刻工具，在该蚀刻工具中，卡盘保持待蚀刻的晶片。定位光学终点设备以测量特征蚀刻深度。电子控制器与光学终点设备和蚀刻工具通信以控制工具通过蚀刻特征部分地减少蚀刻速率并且停止蚀刻工具，使得该特征被蚀刻到期望的深度。

4. 发明申请

WO2012154764A3 METHOD FOR ACHIEVING SMOOTH SIDE WALLS AFTER BOSCH ETCH PROCESS 审中-公开
标题翻译：在铺设过程之后实现平滑侧壁的方法
公开(公告)号：WO2012154764A3
公开(公告)日：2013-01-10
申请号：PCT/US2012036981
申请日：2012-05-09
申请人： LAM RES CORP , WINNICZEK JAROSLAW W , LIN FRANK Y , MILLER ALAN J , XU QING , HEO SEONGJUN , HAM JIN HWAN , YOON SANG JOON , RUSU CAMELIA
发明人： WINNICZEK JAROSLAW W , LIN FRANK Y , MILLER ALAN J , XU QING , HEO SEONGJUN , HAM JIN HWAN , YOON SANG JOON , RUSU CAMELIA
IPC分类号： B81C1/00 , C23F1/00 , H01L21/302
CPC分类号： H01L21/30655 , B81C1/00619 , B81C2201/0112 , H01L21/3086
摘要： A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.
摘要翻译：提供了一种用于在等离子体处理室中蚀刻硅的方法，其具有工作压力和工作偏压。该方法包括：在硅中执行第一垂直蚀刻以产生具有第一深度和侧壁的孔; 在侧壁上进行保护层的沉积; 执行第二垂直蚀刻以将所述孔加深到第二深度并产生第二侧壁，所述第二侧壁包括第一槽，第二槽和峰，所述第一槽对应于所述第一侧壁，所述第二槽对应于第二侧壁，该峰设置在第一槽和第二槽之间; 并进行第三次蚀刻以降低峰值。

5. 发明申请

WO2007133413A3 PHOTORESIST STRIPPING CHAMBER AND METHODS OF ETCHING PHOTORESIST ON SUBSTRATES 审中-公开
标题翻译：光电子剥离室和蚀刻基片上的光刻胶的方法
公开(公告)号：WO2007133413A3
公开(公告)日：2008-10-30
申请号：PCT/US2007010115
申请日：2007-04-25
申请人： LAM RES CORP , CHEBI ROBERT P , WINNICZEK JAROSLAW W , MILLER ALAN J , LO GLADYS S
发明人： CHEBI ROBERT P , WINNICZEK JAROSLAW W , MILLER ALAN J , LO GLADYS S
IPC分类号： H01L21/26 , B44C1/22 , H01L21/42
CPC分类号： H01L21/31138 , H01J37/321 , H01J2237/3342
摘要： Methods of processing a substrate so as to protect an active area include positioning a substrate in an inductively coupled plasma processing chamber, supplying process gas to the chamber, generating plasma from the process gas and processing the substrate so as to protect the active area by maintaining a plasma potential of about 5 to 15 volts at the substrate surface and/or passivating the active area by using a siliane-free process gas including at least one additive effective to form a protective layer on the active area of the substrate wherein the protective layer includes at least one element from the additive which is already present in the active area.
摘要翻译：处理衬底以保护有源区域的方法包括将衬底定位在电感耦合等离子体处理室中，将工艺气体供应到腔室，从处理气体产生等离子体并处理衬底，以通过保持来保护有源区域在衬底表面上具有约5至15伏特的等离子体电位和/或通过使用包含至少一种在衬底的有源区上形成保护层的至少一种添加剂的无硅衬底工艺气体来钝化活性区域，其中保护层包括已经存在于活性区域中的来自添加剂的至少一种元素。

6. 发明申请

WO2012170302A3 METHOD FOR PROVIDING HIGH ETCH RATE 审中-公开
标题翻译：提供高刻蚀速率的方法
公开(公告)号：WO2012170302A3
公开(公告)日：2013-02-07
申请号：PCT/US2012040523
申请日：2012-06-01
申请人： LAM RES CORP , XU QING , RUSU CAMELIA , WINNICZEK JAROSLAW W , LIN FRANK Y , MILLER ALAN J
发明人： XU QING , RUSU CAMELIA , WINNICZEK JAROSLAW W , LIN FRANK Y , MILLER ALAN J
IPC分类号： H01L21/3065
CPC分类号： H01L21/30655 , H01J37/32082 , H01J37/32449 , H01L21/76802 , H01L21/76898
摘要： A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.
摘要翻译：提供了一种用于将特征蚀刻到等离子体处理室中的蚀刻层的方法，其包括多个循环。每个循环包括沉积阶段和蚀刻阶段。沉积阶段包括提供沉积气体流，从等离子体处理室中的沉积气体形成等离子体，在沉积阶段提供第一偏压以提供各向异性沉积，并停止沉积气体流入等离子体处理室。蚀刻阶段包括提供蚀刻气体流，从等离子体处理室中的蚀刻气体形成等离子体，在蚀刻阶段期间提供第二偏压，其中第一偏压大于第二偏压，并停止流动的蚀刻气体进入等离子体处理室。

7. 发明申请

WO2004079783A3 METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS 审中-公开
标题翻译：改进双层门控应用中的配置文件控制和N / P加载的方法
公开(公告)号：WO2004079783A3
公开(公告)日：2005-01-20
申请号：PCT/US2004005944
申请日：2004-02-26
申请人： LAM RES CORP , DEL PUPPO HELENE , LIN FRANK , LEE CHRIS , VAHEDI VAHID , KAMP THOMAS A , MILLER ALAN J
发明人： DEL PUPPO HELENE , LIN FRANK , LEE CHRIS , VAHEDI VAHID , KAMP THOMAS A , MILLER ALAN J
IPC分类号： H01L21/3213 , H01L21/302
CPC分类号： H01L21/32137
摘要： A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.
摘要翻译：提供了一种在等离子体蚀刻室中蚀刻多晶硅栅极结构的方法。该方法开始于限定保护待蚀刻的多晶硅膜的图案。然后，产生等离子体。接下来，蚀刻大部分未被保护的多晶硅膜。然后，引入含硅气体，并且在引入含硅气体的同时蚀刻剩余的多晶硅膜。还提供了一种被配置为在蚀刻工艺期间引入含硅气体的蚀刻室。

8. 发明专利

AU2003275221A8 Apparatus and method for controlling etch depth 未知
公开(公告)号：AU2003275221A8
公开(公告)日：2004-04-19
申请号：AU2003275221
申请日：2003-09-18
申请人： LAM RES CORP
发明人： VENUGOPAL VIJAYAKUMAR C , MILLER ALAN J , KAMP TOM A
IPC分类号： H01L21/00 , H01L21/3065
摘要： An apparatus and method for etching a feature in a wafer with improved depth control and reproducibility is described. The feature is etched at a first etching rate and then at a second etching rate, which is slower than the first etching rate. An optical end point device is used to determine the etching depth and etching is stopped so that the feature has the desired depth. Two different etching rates provides high throughput with good depth control and reproducibility. The apparatus includes an etching tool in which a chuck holds the wafer to be etched. An optical end point device is positioned to measure the feature etch depth. An electronic controller communicates with the optical end point device and the etching tool to control the tool to reduce the etch rate part way through etching the feature and to stop the etching tool, so that that the feature is etched to the desired depth.

9. 发明专利

SG10201601912YA SYSTEMS FOR REMOVING AND REPLACING CONSUMABLE PARTS FROM A SEMICONDUCTOR PROCESS MODULE IN SITU 未知
公开(公告)号：SG10201601912YA
公开(公告)日：2017-05-30
申请号：SG10201601912Y
申请日：2016-03-11
申请人： LAM RES CORP
发明人： TRUSSELL DAVID D , MILLER ALAN J , DAUGHERTY JOHN , PATERSON ALEX
摘要： A cluster tool assembly includes a vacuum transfer module, a process module having a first side connected to the vacuum transfer module. An isolation valve having a first side and a second side, the first side of the isolation valve coupled to a second side of the process module. A replacement station is coupled to the second side of the isolation valve. The replacement station includes an exchange handler and a part buffer. The part buffer includes a plurality of compartments to hold new or used consumable parts. The process module includes a lift mechanism to enable placement of a consumable part installed in the process module to a raised position. The raised position provides access to the exchange handler to enable removal of the consumable part from the process module and store in a compartment of the part buffer. The exchange handler of the replacement station is configured to provide a replacement for the consumable part from the part buffer back to the process module. The lift mechanism is configured to receive the consumable part provided for replacement by the exchange handler and lower the consumable part to an installed position. The replacement by the exchange handler and the process module is conducted while the process module and the replacement station are maintained in a vacuum state.

10. 发明专利

DE60336150D1 METHODE ZUR ÜBERWACHUNG DER ÄTZTIEFE 未知
公开(公告)号：DE60336150D1
公开(公告)日：2011-04-07
申请号：DE60336150
申请日：2003-09-18
申请人： LAM RES CORP
发明人： KAMP TOM A , MILLER ALAN J , VENUGOPAL VIJAYAKUMAR C
IPC分类号： H01L21/3065 , H01L21/00

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