专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080014722A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080014722A1
公开(公告)日：2008-01-17
申请号：US11775130
申请日：2007-07-09
申请人： Young-Soo PARK , Kyoo-Chul CHO , Hee-Sung KIM , Tae-Soo KANG , Sam-Jong CHOI
发明人： Young-Soo PARK , Kyoo-Chul CHO , Hee-Sung KIM , Tae-Soo KANG , Sam-Jong CHOI
IPC分类号： H01L21/20
CPC分类号： H01L21/76254 , H01L27/1207 , H01L27/1211 , H01L29/66795
摘要： Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.
摘要翻译：提供半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体层，第一和第二半导体鳍片，绝缘层和鳍间连接构件。第一和第二半导体散热片放置在半导体层上，具有不同的晶体方向。第一半导体鳍状物与半导体层连接，具有与半导体层相同的晶体方向。绝缘层介于第二半导体鳍片和半导体层之间，并且具有插入第一半导体鳍片的开口。翅片间连接构件将第一半导体翅片和第二半导体翅片在绝缘层上连接起来。

2. 发明申请

US20050016470A1 Susceptor and deposition apparatus including the same 审中-公开
标题翻译：受体和包括其的沉积装置
公开(公告)号：US20050016470A1
公开(公告)日：2005-01-27
申请号：US10898306
申请日：2004-07-26
申请人： Tae-Soo Kang , Soo-Yeol Choi , Kyoo-Chul Cho , Gi-Jung Kim , Jin-Ho Kim , Tae-Yeol Heo
发明人： Tae-Soo Kang , Soo-Yeol Choi , Kyoo-Chul Cho , Gi-Jung Kim , Jin-Ho Kim , Tae-Yeol Heo
IPC分类号： H01L21/205 , C23C16/00 , C23C16/458 , C30B25/12 , C30B31/14
CPC分类号： C23C16/4584 , C30B25/12 , C30B31/14
摘要： A susceptor for use in a deposition apparatus includes a recess in which a wafer is received, and a stress-reducing bumper disposed along the side of the recess. The stress-reducing bumper is of material having ductility at a relatively high temperature. Therefore, when the wafer contacts the stress-reducing bumper, such as may occur due to thermal expansion of the wafer during processing, the force of the impact on the wafer is minimized by an elastic deformation of the stress-reducing bumper. As a result, defects, such as slip dislocations at the outer peripheral edge of the wafer, are prevented.
摘要翻译：用于沉积设备的感受体包括其中容纳晶片的凹部和沿着凹部的侧面设置的减小应力的保险杠。减压保险杠是在较高温度下具有延性的材料。因此，当晶片接触减压保险杠时，例如由于晶片在加工过程中的热膨胀而可能发生的，通过减小应力的保险杠的弹性变形使得对晶片的冲击力最小化。结果，防止了晶片外周边缘处的滑移位错等缺陷。

3. 发明授权

US07675091B2 Semiconductor wafer and method of fabricating the same 有权
标题翻译：半导体晶片及其制造方法
公开(公告)号：US07675091B2
公开(公告)日：2010-03-09
申请号：US11463137
申请日：2006-08-08
申请人： Young-Soo Park , Kyoo-Chul Cho , Shin-Hyeok Han , Tae-Soo Kang
发明人： Young-Soo Park , Kyoo-Chul Cho , Shin-Hyeok Han , Tae-Soo Kang
IPC分类号： H01L29/80
CPC分类号： H01L29/045 , H01L21/76251 , H01L21/84 , H01L27/1203 , H01L29/78687 , H01L29/78696
摘要： Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.
摘要翻译：公开了半导体晶片及其制造方法。半导体晶片由在基底基板上的绝缘层上形成的半导体层构成。半导体层包括以第一晶体取向组织的表面区域和以第二晶体取向组织的另一表面区域。带有单元元件的半导体器件的性能随着载流子的增强而被使用以高结晶取向的高迁移率激活的电荷。半导体晶片通过在第一晶体取向的平面上形成具有第二晶体取向的半导体层，生长外延层，在外延层上形成绝缘层，然后将绝缘层接合到基底来完成。

4. 发明授权

US07573123B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US07573123B2
公开(公告)日：2009-08-11
申请号：US11775130
申请日：2007-07-09
申请人： Young-Soo Park , Kyoo-Chul Cho , Hee-Sung Kim , Tae-Soo Kang , Sam-Jong Choi
发明人： Young-Soo Park , Kyoo-Chul Cho , Hee-Sung Kim , Tae-Soo Kang , Sam-Jong Choi
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L21/76254 , H01L27/1207 , H01L27/1211 , H01L29/66795
摘要： Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.
摘要翻译：提供半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体层，第一和第二半导体鳍片，绝缘层和鳍间连接构件。第一和第二半导体散热片放置在半导体层上，具有不同的晶体方向。第一半导体鳍状物与半导体层连接，具有与半导体层相同的晶体方向。绝缘层介于第二半导体鳍片和半导体层之间，并且具有插入第一半导体鳍片的开口。翅片间连接构件将第一半导体翅片和第二半导体翅片在绝缘层上连接起来。

5. 发明申请

US20070246775A1 SOI SUBSTRATE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译： SOI衬底及其形成方法
公开(公告)号：US20070246775A1
公开(公告)日：2007-10-25
申请号：US11739351
申请日：2007-04-24
申请人： Young-Soo PARK , Kyoo-Chul CHO , Soo-Yeol CHOI , Tae-Soo KANG , Yoon-Hee LEE
发明人： Young-Soo PARK , Kyoo-Chul CHO , Soo-Yeol CHOI , Tae-Soo KANG , Yoon-Hee LEE
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L29/66772 , H01L29/7841 , H01L29/785 , H01L29/7851 , H01L29/78639 , H01L29/7881
摘要： Provided are an SOI substrate, memory devices using the SOI substrate, and a method of manufacturing the same. The SOI substrate includes a thermal oxide layer pattern which minimizes leakage current but allows back biasing and heat dissipation through the substrate. The SOI substrate also includes a metal-gettering site to further minimize leakage current.
摘要翻译：提供了SOI衬底，使用SOI衬底的存储器件及其制造方法。 SOI衬底包括热氧化层图案，其使漏电流最小化，但允许通过衬底的背偏置和散热。 SOI衬底还包括金属吸杂位点以进一步最小化泄漏电流。

6. 发明授权

US07964907B2 Integrated circuit device gate structures 有权
标题翻译：集成电路器件门结构
公开(公告)号：US07964907B2
公开(公告)日：2011-06-21
申请号：US12468414
申请日：2009-05-19
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域在电荷存储区域下的隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

7. 发明申请

US20080246077A1 Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method 审中-公开
标题翻译：通过该方法制造半导体存储器件和半导体存储器件的方法
公开(公告)号：US20080246077A1
公开(公告)日：2008-10-09
申请号：US12012592
申请日：2008-02-04
申请人： Young-Soo Park , Sam-Jong Choi , Kyoo-Chul Cho , Tae-Soo Kang
发明人： Young-Soo Park , Sam-Jong Choi , Kyoo-Chul Cho , Tae-Soo Kang
IPC分类号： H01L27/108 , H01L21/425
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/26506 , H01L29/40114 , H01L29/42332
摘要： In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure.
摘要翻译：在通过该方法制造半导体存储器件和半导体存储器件的方法中，该方法包括形成包括具有离子注入层的第一介电层和没有离子注入层的第二电介质层的多层电介质结构，在半导体衬底上; 通过热处理多层电介质结构，通过离子注入层的离子扩散来在第一和第二电介质层中形成纳米晶体; 以及在所述多层电介质结构上形成栅电极。

8. 发明申请

US20050259246A1 Apparatus for inspecting a surface and methods thereof 审中-公开
标题翻译：用于检查表面的装置及其方法
公开(公告)号：US20050259246A1
公开(公告)日：2005-11-24
申请号：US11133367
申请日：2005-05-20
申请人： Tae-Soo Kang , Kyoo-Chul Cho , Soo-Yeol Choi , Sam-Dong Choi
发明人： Tae-Soo Kang , Kyoo-Chul Cho , Soo-Yeol Choi , Sam-Dong Choi
IPC分类号： H01L21/66 , G01N21/47 , G01N21/88 , G01N21/95
CPC分类号： G01N21/47 , G01N21/9501
摘要： An apparatus and method for detecting a surface status. The method includes generating first and second pulse sequences and irradiating the first and second pulse sequences into a given surface. Light from the first and second pulses may be scattered by the given surface and analyzed to determine the status of the given surface. The apparatus includes a device for generating pulses which contact a given surface at different incident angles. The light scattered from the pulses may be analyzed at a determining part to determine a status of the given surface. In another embodiment, the method includes generating first and second pulse sequences and adjusting a path of at least a portion of at least one of the first and second pulse sequences such that the first and second pulse sequences are incident upon a given surface at different incident angles.
摘要翻译：一种用于检测表面状态的装置和方法。该方法包括产生第一和第二脉冲序列并将第一和第二脉冲序列照射到给定的表面中。来自第一和第二脉冲的光可以被给定的表面散射并且被分析以确定给定表面的状态。该装置包括用于产生以不同入射角接触给定表面的脉冲的装置。可以在确定部分分析从脉冲散射的光以确定给定表面的状态。在另一个实施例中，该方法包括产生第一和第二脉冲序列并且调整第一和第二脉冲序列中的至少一个的至少一部分的路径，使得第一和第二脉冲序列在不同事件处入射到给定表面上角度。

9. 发明申请

US20090236655A1 INTEGRATED CIRCUIT DEVICE GATE STRUCTURES 有权
标题翻译：集成电路设计门结构
公开(公告)号：US20090236655A1
公开(公告)日：2009-09-24
申请号：US12468414
申请日：2009-05-19
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域在电荷存储区域下的隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

10. 发明申请

US20090096014A1 NONVOLATILE MEMORY DEVICES THAT INCLUDE AN INSULATING FILM WITH NANOCRYSTALS EMBEDDED THEREIN AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：包含嵌入其中的纳米晶体的绝缘膜的非易失性存储器件及其制造方法
公开(公告)号：US20090096014A1
公开(公告)日：2009-04-16
申请号：US12137109
申请日：2008-06-11
申请人： Sam-Jong Choi , Kyoo-Chul Cho , Jung-Sik Choi , Hee-sung Kim , Tae-Soo Kang , Yoon-Hee Lee
发明人： Sam-Jong Choi , Kyoo-Chul Cho , Jung-Sik Choi , Hee-sung Kim , Tae-Soo Kang , Yoon-Hee Lee
IPC分类号： H01L29/792 , H01L21/31
CPC分类号： H01L21/02175 , H01L21/022 , H01L21/02356 , H01L21/31155 , H01L21/316 , H01L27/115 , H01L29/40114 , H01L29/42332 , H01L29/513 , H01L29/7883 , H01L29/7885
摘要： A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with improved reliability.
摘要翻译：非易失性存储器件包括半导体衬底，设置在半导体衬底上的电荷陷阱结构，其包括绝缘膜和嵌入在绝缘膜中的多个碳纳米晶体，以及设置在电荷捕获结构上的栅极。非易失性存储器件可以具有提高的可靠性的存储滞后特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式