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1. 发明授权

US07728375B2 Semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US07728375B2
公开(公告)日：2010-06-01
申请号：US12219358
申请日：2008-07-21
申请人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
发明人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10855 , H01L27/10888
摘要： Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.
摘要翻译：示例性实施例涉及半导体存储器件和形成半导体存储器件的方法。半导体存储器件可以包括半导体衬底上的第一层间绝缘层。位线可以在第一层间绝缘层上沿第一方向布置。位线接触焊盘可以设置在第一层间绝缘层中并电连接到位线。存储接触焊盘可以设置在第一层间绝缘层中。位线接触焊盘的顶表面可以低于存储触点焊盘的顶表面。

2. 发明申请

US20090026515A1 Semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20090026515A1
公开(公告)日：2009-01-29
申请号：US12219358
申请日：2008-07-21
申请人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
发明人： Kyoung-Sub Shin , Cheol-Kyu Lee , Sung-il Cho , Young-Kyu Cho
IPC分类号： H01L29/94 , H01L21/4763
CPC分类号： H01L28/91 , H01L27/10855 , H01L27/10888
摘要： Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.
摘要翻译：示例性实施例涉及半导体存储器件和形成半导体存储器件的方法。半导体存储器件可以包括半导体衬底上的第一层间绝缘层。位线可以在第一层间绝缘层上沿第一方向布置。位线接触焊盘可以设置在第一层间绝缘层中并且电连接到位线。存储接触焊盘可以设置在第一层间绝缘层中。位线接触焊盘的顶表面可以低于存储触点焊盘的顶表面。

3. 发明授权

US09899404B2 Semiconductor device 有权
公开(公告)号：US09899404B2
公开(公告)日：2018-02-20
申请号：US14957099
申请日：2015-12-02
申请人： Jin-Hyuk Yoo , Dae-Hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
发明人： Jin-Hyuk Yoo , Dae-Hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
IPC分类号： H01L29/76 , H01L27/1157 , H01L23/48 , H01L27/11573 , H01L27/11582 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L29/06
CPC分类号： H01L27/1157 , H01L23/48 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

4. 发明授权

US08669622B2 Non-volatile semiconductor devices and methods of manufacturing non-volatile semiconductor devices 有权
标题翻译：非挥发性半导体器件和制造非易失性半导体器件的方法
公开(公告)号：US08669622B2
公开(公告)日：2014-03-11
申请号：US13157753
申请日：2011-06-10
申请人： Hak-Sun Lee , Kyoung-Sub Shin
发明人： Hak-Sun Lee , Kyoung-Sub Shin
IPC分类号： H01L21/70
CPC分类号： H01L27/11573
摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.
摘要翻译：非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极阻挡层图案。控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

5. 发明申请

US20110284163A1 PLASMA PROCESSING APPARATUS 审中-公开
标题翻译：等离子体加工设备
公开(公告)号：US20110284163A1
公开(公告)日：2011-11-24
申请号：US13086475
申请日：2011-04-14
申请人： Jun-Ho Yoon , Kyoung-Sub Shin , Woo-Seok Kim , Dong-Kwon Kim , Hyung-Yong Kim , Yong-Ho Jeon
发明人： Jun-Ho Yoon , Kyoung-Sub Shin , Woo-Seok Kim , Dong-Kwon Kim , Hyung-Yong Kim , Yong-Ho Jeon
IPC分类号： H01L21/00 , C23F1/08
CPC分类号： H01L21/67069 , H01J37/32935 , H01J37/32972
摘要： A plasma processing apparatus includes a chamber for processing a substrate. A plasma generator is provided to generate plasma within the chamber. A window is provided in a sidewall of the chamber, and the window transmits light from the plasma within the chamber. A photocatalytic layer is provided on an inner surface of the window such that the photocatalytic layer is activated as a result of exposure to light from the plasma to decompose a residual product on the inner surface of the window.
摘要翻译：等离子体处理装置包括用于处理基板的室。提供等离子体发生器以在腔室内产生等离子体。窗口设置在室的侧壁中，并且窗口从腔室内的等离子体透射光。在窗的内表面上提供光催化层，使得光催化层由于暴露于等离子体的光而被激活，从而在窗的内表面上分解残留产物。

6. 发明授权

US08883588B2 Semiconductor devices and methods of manufacturing the semiconductor devices 有权
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：US08883588B2
公开(公告)日：2014-11-11
申请号：US13599233
申请日：2012-08-30
申请人： Sung-Soo Ahn , O Ik Kwon , Bum-Soo Kim , Hyun-Sung Kim , Kyoung-Sub Shin , Min-Kyung Yun , Seung-Pil Chung , Won-Bong Jung
发明人： Sung-Soo Ahn , O Ik Kwon , Bum-Soo Kim , Hyun-Sung Kim , Kyoung-Sub Shin , Min-Kyung Yun , Seung-Pil Chung , Won-Bong Jung
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/7883 , H01L21/7682 , H01L27/11521 , H01L29/42324 , H01L29/42364 , H01L29/66825 , H01L29/7881
摘要： A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底的上表面上形成隧道绝缘层，在隧道绝缘层的上表面上形成栅极图案，在栅极图案的侧壁上形成覆盖层图案，并且在隧道绝缘层的上表面，蚀刻未被栅极图案或覆盖层图案覆盖的隧道绝缘层的一部分以形成隧道绝缘层图案，并且在衬底的上表面上形成第一绝缘层以覆盖栅极图案，覆盖层图案和隧道绝缘层图案，其中第一绝缘层在封盖层图案之间具有气隙。

7. 发明授权

US08871591B2 Methods of manufacturing a vertical type semiconductor device 有权
标题翻译：制造垂直型半导体器件的方法
公开(公告)号：US08871591B2
公开(公告)日：2014-10-28
申请号：US13600025
申请日：2012-08-30
申请人： Yong-Hyun Kwon , Dae-Hyun Jang , Seong-Soo Lee , Kyoung-Sub Shin
发明人： Yong-Hyun Kwon , Dae-Hyun Jang , Seong-Soo Lee , Kyoung-Sub Shin
IPC分类号： H01L21/336
CPC分类号： H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L27/11556 , H01L27/11575 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.
摘要翻译：根据本发明构思的示例性实施例，一种方法包括在基板上的单元图案之间形成单元图案和绝缘夹层。在最上面的单元图案上形成包括初始接触孔和预接触孔的上绝缘层。形成第一反射限制层图案和第一光致抗蚀剂层图案，用于暴露第一初步接触孔，同时覆盖初始和初步接触孔的入口部分。在第一初步接触孔下方的层上进行第一蚀刻处理，以在比第一预接触孔的底部低的位置处露出电池图案。重复第一反射限制层图案和第一光致抗蚀剂层图案的侧壁部分的部分去除处理以及通过预接触孔的底部的暴露层上的蚀刻工艺，以形成具有不同深度的接触孔。

8. 发明申请

US20130320486A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130320486A1
公开(公告)日：2013-12-05
申请号：US13786853
申请日：2013-03-06
申请人： Jin-Hyuk YOO , Dae-hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
发明人： Jin-Hyuk YOO , Dae-hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
IPC分类号： H01L23/48
CPC分类号： H01L27/1157 , H01L23/48 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.
摘要翻译：提供一种半导体器件。半导体器件包括设置在半导体衬底上的导电图案。设置在导电图案上并且彼此位于相同水平面的第一和第二导电线。隔离图案设置在第一和第二导线之间。提供穿过第一导线和导电图案的第一垂直结构。提供穿过第二导线和导电图案的第二垂直结构。提供穿过导电图案并与隔离图案接触的辅助图案。

9. 发明授权

US08420453B2 Method of forming active region structure 有权
标题翻译：形成有源区结构的方法
公开(公告)号：US08420453B2
公开(公告)日：2013-04-16
申请号：US12801074
申请日：2010-05-20
申请人： Jun-Ho Yoon , Byeong-Soo Kim , Kyoung-Sub Shin , Hong Cho , Hyung-Yong Kim
发明人： Jun-Ho Yoon , Byeong-Soo Kim , Kyoung-Sub Shin , Hong Cho , Hyung-Yong Kim
IPC分类号： H01L21/82
CPC分类号： H01L21/308 , H01L21/76229 , H01L27/0207 , H01L27/1052 , H01L27/10894 , H01L27/11526
摘要： A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.
摘要翻译：形成有源区结构的方法包括制备包括单元阵列区域和外围电路区域的半导体衬底，在半导体衬底的单元阵列区域中形成初级电池活性区域，并在初级电池活性区域中形成电池活性区域以及半导体衬底的外围电路区域中的至少一个外围有源区域，使得初步电池活性区域，电池活性区域和至少一个外围有源区域与半导体衬底一体地形成并从半导体基质。

10. 发明申请

US20100237401A1 GATE STRUCTURES OF SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的门结构
公开(公告)号：US20100237401A1
公开(公告)日：2010-09-23
申请号：US12726836
申请日：2010-03-18
申请人： JEONG-DONG CHOE , Kyoung-Sub Shin , Kyoung-Hwan Yeo
发明人： JEONG-DONG CHOE , Kyoung-Sub Shin , Kyoung-Hwan Yeo
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/40117 , H01L29/513
摘要： Gate structures of semiconductor devices and methods of forming gate structures of semiconductor devices are provided. A first insulating pattern may be disposed on an active region of a semiconductor substrate. A data storage pattern may be disposed on the first insulating pattern. A second insulating pattern may be disposed on the data storage pattern and may contact the data storage pattern. A first conductive pattern may conform to the second insulating pattern and to sidewalls of a mold comprising the second insulating pattern. A second conductive pattern may be disposed within a cavity defined by the first conductive pattern. Spacers may be formed on sidewalls of at least one of the first insulating pattern, the data storage pattern, the second insulating pattern, and the conductive pattern.
摘要翻译：提供了半导体器件的栅极结构和形成半导体器件的栅极结构的方法。第一绝缘图案可以设置在半导体衬底的有源区上。数据存储图案可以设置在第一绝缘图案上。第二绝缘图案可以设置在数据存储图案上并且可以接触数据存储图案。第一导电图案可以符合第二绝缘图案以及包括第二绝缘图案的模具的侧壁。第二导电图案可以设置在由第一导电图案限定的空腔内。间隔件可以形成在第一绝缘图案，数据存储图案，第二绝缘图案和导电图案中的至少一个的侧壁上。

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