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1. 发明授权

US08815676B2 Three dimensional semiconductor memory device and method of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08815676B2
公开(公告)日：2014-08-26
申请号：US13671948
申请日：2012-11-08
申请人： Sang-Ryol Yang , Yoo-Chul Kong , Jung-Ho Kim , Jin-Gyun Kim , Jae-Jin Shin , Ji-Hoon Choi
发明人： Sang-Ryol Yang , Yoo-Chul Kong , Jung-Ho Kim , Jin-Gyun Kim , Jae-Jin Shin , Ji-Hoon Choi
IPC分类号： H01L21/00
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.
摘要翻译：形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

2. 发明授权

US08557661B2 Methods of manufacturing a semiconductor device and a semiconductor memory device thereby 有权
标题翻译：因此制造半导体器件和半导体存储器件的方法
公开(公告)号：US08557661B2
公开(公告)日：2013-10-15
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
发明人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

3. 发明申请

US20120187471A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MEMORY DEVICE THEREBY 有权
标题翻译：制造半导体器件的方法和半导体存储器件
公开(公告)号：US20120187471A1
公开(公告)日：2012-07-26
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
发明人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
IPC分类号： H01L29/78 , H01L21/336 , H01L21/308
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

4. 发明授权

US09899404B2 Semiconductor device 有权
公开(公告)号：US09899404B2
公开(公告)日：2018-02-20
申请号：US14957099
申请日：2015-12-02
申请人： Jin-Hyuk Yoo , Dae-Hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
发明人： Jin-Hyuk Yoo , Dae-Hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
IPC分类号： H01L29/76 , H01L27/1157 , H01L23/48 , H01L27/11573 , H01L27/11582 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L29/06
CPC分类号： H01L27/1157 , H01L23/48 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

5. 发明授权

US07312117B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07312117B2
公开(公告)日：2007-12-25
申请号：US11193788
申请日：2005-07-28
申请人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
发明人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.
摘要翻译：半导体器件包括在限定在衬底上的有源区上沿第一方向延伸的字线结构。第一和第二接触垫形成在字线结构两侧的有源区上。位线结构电连接到第一接触焊盘并沿基本垂直于第一方向的第二方向延伸。在具有位线结构的基板上形成绝缘层结构。存储节点接触插头通过绝缘层结构电连接到第二接触垫。作为电容器的一部分的存储节点电极形成在存储节点接触插头上。存储节点接触插头具有下部和具有比下部的宽度宽的上部，其垂直方向垂直于第一和第二方向。

6. 发明申请

US20060022256A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060022256A1
公开(公告)日：2006-02-02
申请号：US11193788
申请日：2005-07-28
申请人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
发明人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
IPC分类号： H01L29/788
CPC分类号： H01L28/91 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.
摘要翻译：半导体器件包括在限定在衬底上的有源区上沿第一方向延伸的字线结构。第一和第二接触垫形成在字线结构两侧的有源区上。位线结构电连接到第一接触焊盘并沿基本垂直于第一方向的第二方向延伸。在具有位线结构的基板上形成绝缘层结构。存储节点接触插头通过绝缘层结构电连接到第二接触垫。作为电容器的一部分的存储节点电极形成在存储节点接触插头上。存储节点接触插头具有下部部分和具有比下部部分宽的宽度的上部部分，垂直方向垂直于第一和第二方向。

7. 发明申请

US20160111431A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20160111431A1
公开(公告)日：2016-04-21
申请号：US14957099
申请日：2015-12-02
申请人： Jin-Hyuk Yoo , Dae-Hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
发明人： Jin-Hyuk Yoo , Dae-Hyun Jang , Yoo-Chul Kong , Kyoung-Sub Shin
IPC分类号： H01L27/115 , H01L29/06 , H01L23/528
CPC分类号： H01L27/1157 , H01L23/48 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

8. 发明申请

US20130065369A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20130065369A1
公开(公告)日：2013-03-14
申请号：US13671948
申请日：2012-11-08
申请人： Sang-Ryol Yang , Yoo-Chul Kong , Jung-Ho Kim , Jin-Gyun Kim , Jae-Jin Shin , Ji-Hoon Choi
发明人： Sang-Ryol Yang , Yoo-Chul Kong , Jung-Ho Kim , Jin-Gyun Kim , Jae-Jin Shin , Ji-Hoon Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.
摘要翻译：形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

9. 发明申请

US20120083077A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120083077A1
公开(公告)日：2012-04-05
申请号：US13228433
申请日：2011-09-08
申请人： Sang-Ryol Yang , Yoo-Chul Kong , Jin-Gyun Kim , Jae-Jin Shin , Jung-Ho Kim , Ji-Hoon Choi
发明人： Sang-Ryol Yang , Yoo-Chul Kong , Jin-Gyun Kim , Jae-Jin Shin , Jung-Ho Kim , Ji-Hoon Choi
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.
摘要翻译：形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

10. 发明申请

US20080061352A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080061352A1
公开(公告)日：2008-03-13
申请号：US11935160
申请日：2007-11-05
申请人： Doo-Young LEE , Yoo-Chul KONG , Jong-Chul PARK , Sang-Sup JEONG
发明人： Doo-Young LEE , Yoo-Chul KONG , Jong-Chul PARK , Sang-Sup JEONG
IPC分类号： H01L29/788
CPC分类号： H01L28/91 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.
摘要翻译：半导体器件包括在限定在衬底上的有源区上沿第一方向延伸的字线结构。第一和第二接触垫形成在字线结构两侧的有源区上。位线结构电连接到第一接触焊盘并沿基本垂直于第一方向的第二方向延伸。在具有位线结构的基板上形成绝缘层结构。存储节点接触插头通过绝缘层结构电连接到第二接触垫。作为电容器的一部分的存储节点电极形成在存储节点接触插头上。存储节点接触插头具有下部和具有比下部的宽度宽的上部，其垂直方向垂直于第一和第二方向。

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