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1. 发明授权

US06387460B1 Glass panel 失效
标题翻译：玻璃面板
公开(公告)号：US06387460B1
公开(公告)日：2002-05-14
申请号：US09445839
申请日：2000-04-03
申请人： Kyoichi Shukuri , Hideo Yoshizawa , Naoto Horiguchi , Osamu Asano , Keiichiro Okajima , Tomonori Miura , Masao Misonou , Seiichiro Honjo
发明人： Kyoichi Shukuri , Hideo Yoshizawa , Naoto Horiguchi , Osamu Asano , Keiichiro Okajima , Tomonori Miura , Masao Misonou , Seiichiro Honjo
IPC分类号： C03C2706
CPC分类号： E06B3/6612 , E06B3/66304 , Y02A30/25 , Y02B80/24
摘要： A glass panel including a pair of first and second glass sheets (1A, 1B) disposed with sheet faces thereof opposed to each other, a plurality of spacers (5) being interposed between the pair of glass sheets (1A, 1B) for forming a space (4) therebetween; and a sealing material (S) for bonding peripheral edges (3) of the glass sheets (1A, 1B) together for sealing the space (4), the sealing material having a lower fusing temperature than the softening point of the glass sheets (1A, 1B). Each spacer (5) is formed by disposing spacer-forming paste (11) in a predetermined shape on the sheet face of the glass sheet (1A, 1B). Or, the spacer (5) comprises a plurality of spacer bodies (51) two-dimensionally interconnected to each other via a connecting member (52).
摘要翻译：一种玻璃面板，包括一对第一和第二玻璃板（1A，1B），所述第一和第二玻璃板（1A，1B）设置成彼此相对的板表面，多个间隔件（5）插入在所述一对玻璃板（1A，1B）之间，用于形成空间（4）; 以及用于将玻璃板（1A，1B）的周边边缘（3）接合在一起用于密封空间（4）的密封材料（S），具有比玻璃板（1A）的软化点低的定影温度的密封材料，1B）。每个间隔物（5）通过在玻璃板（1A，1B）的表面上设置预定形状的间隔物形成膏（11）而形成。或者，间隔件（5）包括经由连接构件（52）彼此二维地互连的多个间隔体（51）。

2. 发明授权

US06479112B1 Glass panel and method of manufacturing thereof and spacers used for glass panel 失效
标题翻译：玻璃面板及其制造方法以及用于玻璃面板的间隔物
公开(公告)号：US06479112B1
公开(公告)日：2002-11-12
申请号：US09445153
申请日：2000-02-25
申请人： Kyoichi Shukuri , Hideo Yoshizawa , Naoto Horiguchi , Osamu Asano , Keiichiro Okajima , Tomonori Miura
发明人： Kyoichi Shukuri , Hideo Yoshizawa , Naoto Horiguchi , Osamu Asano , Keiichiro Okajima , Tomonori Miura
IPC分类号： E06B324
CPC分类号： E06B3/6612 , E06B3/66304 , Y02A30/25 , Y02B80/24
摘要： A glass panel, its manufacturing method and a spacer for use in the glass panel. In the glass panel, a plurality of spacers (3) are formed between and along a first opposing face (2A) of a first glass sheet (1A) and a second opposing face (2B) of a second glass sheet (1B) so as to form a space (C) therebetween, and a sealing material (6) is provided at peripheral edge (1a) of the first glass sheet (1A) and the second glass sheet (1B) for maintaining the space (C) gas-tight. The plurality of such spacers (3) having, at one side thereof, contact portions (5) capable of coming into contact with the first opposing face (2A) are provided on the second opposing face (2B). The contact portions (5) and the first opposing face (2A) are movable relative to each other.
摘要翻译：玻璃面板，其制造方法和用于玻璃面板的间隔件。在玻璃面板中，沿第一玻璃板（1A）的第一相对面（2A）和第二玻璃板（1B）的第二相对面（2B）之间形成多个间隔件（3）在它们之间形成空间（C），并且在第一玻璃板（1A）和第二玻璃板（1B）的周缘（1a）处设置密封材料（6），用于将空间（C）保持在气密性。在第二相对面（2B）上设置有多个这样的间隔件（3），其一侧具有能够与第一相对面（2A）接触的接触部分（5）。接触部分（5）和第一相对面（2A）可相对于彼此移动。

3. 发明授权

US06210763B1 Double-glazing unit 失效
标题翻译：双层玻璃单元
公开(公告)号：US06210763B1
公开(公告)日：2001-04-03
申请号：US09297815
申请日：1999-05-04
申请人： Hidemi Katoh , Naoto Horiguchi , Masao Misonou
发明人： Hidemi Katoh , Naoto Horiguchi , Masao Misonou
IPC分类号： E06B324
CPC分类号： E06B3/66304 , Y02A30/25 , Y02B80/24
摘要： In a double glazing including a pair of glass sheets 1, a plurality of spacers 2 disposed between opposed sheet faces of the glass sheets 1 by a predetermined pitch, and a sealing member 4 interposed between the glass sheets 1 along the entire peripheries thereof, with a space V between the glass sheets being sealed in a vacuum condition, each spacer 2 is formed so as to maintain a predetermined distance between the glass sheets when subjected to a static normal external pressure normally applied thereto in the direction of sheet thickness and also to relieve stress through plastic deformation when subjected to an impact dynamically applied in the sheet thickness direction.
摘要翻译：在包括一对玻璃板1的双层玻璃中，以预定间距设置在玻璃板1的相对的板表面之间的多个间隔件2和沿其整个周边插入在玻璃板1之间的密封构件4与玻璃板之间的空间V在真空条件下被密封，每个间隔件2形成为当经受在板厚方向上通常施加到其上的静态正常外部压力时，玻璃板之间保持预定距离，并且还可以当受到在板厚度方向上动态施加的冲击时，通过塑性变形来缓解应力。

4. 发明授权

US07468297B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07468297B2
公开(公告)日：2008-12-23
申请号：US11099699
申请日：2005-04-06
申请人： Toshiro Futatsugi , Naoto Horiguchi , Ken-ichi Okabe , Kenichi Hikazutani
发明人： Toshiro Futatsugi , Naoto Horiguchi , Ken-ichi Okabe , Kenichi Hikazutani
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L27/0629 , H01L29/94
摘要： A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.
摘要翻译：一种制造半导体器件的方法，包括：通过以第一剂量注入杂质，在半导体衬底的第一区域中形成第一杂质扩散区域作为电容器的下电极; 通过以第二剂量注入杂质，在半导体衬底的端部的第二区域中形成第二杂质扩散区; 并通过热氧化法形成在第一杂质扩散区上具有第一厚度的电容器绝缘膜，并形成第二厚度比第二区域厚的第二厚度的氧化膜。

5. 发明授权

US07235470B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07235470B2
公开(公告)日：2007-06-26
申请号：US10806247
申请日：2004-03-23
申请人： Naoto Horiguchi
发明人： Naoto Horiguchi
IPC分类号： H01L21/265
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1079 , H01L29/665 , H01L29/7833
摘要： A semiconductor device is provided, which aims to reduce the standby power thereof by reducing the leak between a body and a drain with restraining the effect on a threshold voltage, in order to actualize the highly reliable semiconductor device. When extension regions are formed, an n-type impurity less diffusive than phosphorus (P+), for example, arsenic (As+) is used as an impurity. In addition to ordinary ion implantation with high dose (high concentration) and low acceleration energy, As+ ions are implanted with low dose and high acceleration energy.
摘要翻译：提供一种半导体器件，其目的是通过抑制对阈值电压的影响来减少身体和漏极之间的泄漏来降低其待机功率，以实现高度可靠的半导体器件。当形成扩展区时，使用比磷（P + SUP）更难扩散的n型杂质，例如砷（As + SUP））作为杂质。除了具有高剂量（高浓度）和低加速能量的普通离子注入之外，以低剂量和高加速能量注入As + +离子。

6. 发明授权

US06774430B2 Non-volatile semiconductor memory device having gate insulating film with thick end sections 有权
标题翻译：具有栅极绝缘膜的非易失性半导体存储器件具有较厚的端部
公开(公告)号：US06774430B2
公开(公告)日：2004-08-10
申请号：US09984215
申请日：2001-10-29
申请人： Naoto Horiguchi , Toshiro Futatsugi
发明人： Naoto Horiguchi , Toshiro Futatsugi
IPC分类号： H01L29788
CPC分类号： H01L29/7885 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A non-volatile semiconductor memory comprising a semiconductor substrate, a gate insulating film formed on the substrate, and having a thin central section and thick end sections, a floating gate formed on the rate insulating film, an inter-electrode insulating film formed on the floating gate, a control gate formed on the inter-electrode insulating film, and source/drain regions formed in the substrate on both sides of the floating sate and having extensions extending under the thick end sections of the floating gate, and separated from the thin central section of the gate insulating film, wherein the thin central section enables tunneling of carriers at a low applied voltage, and thick end sections prevent tunneling of stored charges to the extensions and enhance retention of the stored charges.
摘要翻译：一种非易失性半导体存储器，包括半导体衬底，形成在衬底上的栅极绝缘膜，并且具有薄的中心部分和厚的端部部分，形成在速率绝缘膜上的浮动栅极，形成在所述衬底上的电极间绝缘膜浮置栅极，形成在电极间绝缘膜上的控制栅极以及形成在浮动栅极两侧的基板中的源极/漏极区域，并且具有在浮动栅极的厚端部下方延伸的延伸部，并且与薄膜栅极绝缘膜的中心部分，其中薄的中心部分能够使载体在低施加电压下隧道化，并且厚端部部分防止存储的电荷隧道到延伸部并且增强存储的电荷的保留。

7. 发明授权

US06462374B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06462374B2
公开(公告)日：2002-10-08
申请号：US09814000
申请日：2001-03-22
申请人： Tatsuya Usuki , Naoto Horiguchi
发明人： Tatsuya Usuki , Naoto Horiguchi
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： To provide a semiconductor device which can retain information for a long period of time even in a case that the tunnel insulation film is thin. A semiconductor device comprises a first insulation film 14 formed on a semiconductor substrate 10, a floating gate electrode 22 formed on the first insulation film, a second insulation 24 film formed on the floating gate electrode, and a control gate electrode 26 formed on the second insulation film. A depletion layer is formed in the floating gate electrode near the first insulation film in a state that no voltage is applied between the floating gate electrode and the semiconductor substrate.
摘要翻译：即使在隧道绝缘膜薄的情况下，也能够长时间地保持信息的半导体装置。半导体器件包括形成在半导体衬底10上的第一绝缘膜14，形成在第一绝缘膜上的浮栅电极22，形成在浮栅电极上的第二绝缘层24，以及形成在第二绝缘膜上的控制栅极26 绝缘膜。在浮置栅电极和半导体基板之间没有施加电压的状态下，在第一绝缘膜附近的浮置栅电极中形成耗尽层。

8. 发明授权

US5936258A Optical semiconductor memory device and read/write method therefor 失效
标题翻译：光半导体存储器件及其读/写方法
公开(公告)号：US5936258A
公开(公告)日：1999-08-10
申请号：US632153
申请日：1996-04-15
申请人： Kenichi Imamura , Shun-ichi Muto , Naoto Horiguchi , Yoshihiro Sugiyama , Yoshiaki Nakata
发明人： Kenichi Imamura , Shun-ichi Muto , Naoto Horiguchi , Yoshihiro Sugiyama , Yoshiaki Nakata
IPC分类号： G11C7/00 , G11C13/04 , H01L29/12 , H01L31/0304 , H01L31/10 , H01L31/105
CPC分类号： B82Y10/00 , G11C13/04 , G11C7/005 , H01L29/127 , G11C2216/08
摘要： A wavelength-domain-multiplication memory comprises a first semiconductor layer including a first conductivity type impurity, a carrier barrier semiconductor layer formed on the first semiconductor layer, and quantum dots formed in the carrier barrier semiconductor layer.
摘要翻译：波长域倍增存储器包括第一半导体层，包括第一导电型杂质，形成在第一半导体层上的载流子阻挡半导体层，以及形成在载流子阻挡半导体层中的量子点。

9. 发明授权

US06828629B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06828629B2
公开(公告)日：2004-12-07
申请号：US10768064
申请日：2004-02-02
申请人： Naoto Horiguchi
发明人： Naoto Horiguchi
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/6656 , H01L29/7833
摘要： A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.
摘要翻译：在半导体衬底的表面上形成P型袋层，形成厚度为10nm或以下的侧壁绝缘膜，并且将P注入到其中以形成N型延伸层 p型袋层的表面部分。然后，形成侧壁绝缘膜，并注入P，从而形成N型源极和漏极扩散层。具有比用于形成袋层的常规使用的As更大的扩散系数的P可以成功地调节通道附近的强电场，并且因此可以减少漏极和半导体之间的漏电流从而降低漏电流，即使栅极长度减小到100nm以下。

10. 发明授权

US06815759B2 Semiconductor memory with floating gate type FET 有权
标题翻译：具有浮栅型FET的半导体存储器
公开(公告)号：US06815759B2
公开(公告)日：2004-11-09
申请号：US09726386
申请日：2000-12-01
申请人： Naoto Horiguchi , Tatsuya Usuki , Kenichi Goto
发明人： Naoto Horiguchi , Tatsuya Usuki , Kenichi Goto
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , G11C16/0416 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： A tunneling insulating film is formed on the partial surface area of a semiconductor substrate. A floating gate electrode is formed on the tunneling insulating film. A gate insulating film covers the side wall of the floating gate electrode and a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A first control gate electrode is disposed on the gate insulating film over the side wall of the floating gate electrode and over a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A pair of impurity doped regions is formed in a surface layer of the semiconductor substrate on both sides of a gate structure including the floating gate structure and first control gate structure.

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