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1. 发明授权

US07468297B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07468297B2
公开(公告)日：2008-12-23
申请号：US11099699
申请日：2005-04-06
申请人： Toshiro Futatsugi , Naoto Horiguchi , Ken-ichi Okabe , Kenichi Hikazutani
发明人： Toshiro Futatsugi , Naoto Horiguchi , Ken-ichi Okabe , Kenichi Hikazutani
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L27/0629 , H01L29/94
摘要： A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.
摘要翻译：一种制造半导体器件的方法，包括：通过以第一剂量注入杂质，在半导体衬底的第一区域中形成第一杂质扩散区域作为电容器的下电极; 通过以第二剂量注入杂质，在半导体衬底的端部的第二区域中形成第二杂质扩散区; 并通过热氧化法形成在第一杂质扩散区上具有第一厚度的电容器绝缘膜，并形成第二厚度比第二区域厚的第二厚度的氧化膜。

2. 发明授权

US06774430B2 Non-volatile semiconductor memory device having gate insulating film with thick end sections 有权
标题翻译：具有栅极绝缘膜的非易失性半导体存储器件具有较厚的端部
公开(公告)号：US06774430B2
公开(公告)日：2004-08-10
申请号：US09984215
申请日：2001-10-29
申请人： Naoto Horiguchi , Toshiro Futatsugi
发明人： Naoto Horiguchi , Toshiro Futatsugi
IPC分类号： H01L29788
CPC分类号： H01L29/7885 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A non-volatile semiconductor memory comprising a semiconductor substrate, a gate insulating film formed on the substrate, and having a thin central section and thick end sections, a floating gate formed on the rate insulating film, an inter-electrode insulating film formed on the floating gate, a control gate formed on the inter-electrode insulating film, and source/drain regions formed in the substrate on both sides of the floating sate and having extensions extending under the thick end sections of the floating gate, and separated from the thin central section of the gate insulating film, wherein the thin central section enables tunneling of carriers at a low applied voltage, and thick end sections prevent tunneling of stored charges to the extensions and enhance retention of the stored charges.
摘要翻译：一种非易失性半导体存储器，包括半导体衬底，形成在衬底上的栅极绝缘膜，并且具有薄的中心部分和厚的端部部分，形成在速率绝缘膜上的浮动栅极，形成在所述衬底上的电极间绝缘膜浮置栅极，形成在电极间绝缘膜上的控制栅极以及形成在浮动栅极两侧的基板中的源极/漏极区域，并且具有在浮动栅极的厚端部下方延伸的延伸部，并且与薄膜栅极绝缘膜的中心部分，其中薄的中心部分能够使载体在低施加电压下隧道化，并且厚端部部分防止存储的电荷隧道到延伸部并且增强存储的电荷的保留。

3. 发明授权

US4889831A Method of forming a high temperature stable ohmic contact to a III-V substrate 失效
标题翻译：形成与III-V基板的高温稳定欧姆接触的方法
公开(公告)号：US4889831A
公开(公告)日：1989-12-26
申请号：US126339
申请日：1987-11-30
申请人： Kazuaki Ishii , Toshiro Futatsugi , Toshio Oshima , Toshio Fujii , Naoki Yokoyama , Akihiro Shibatomi
发明人： Kazuaki Ishii , Toshiro Futatsugi , Toshio Oshima , Toshio Fujii , Naoki Yokoyama , Akihiro Shibatomi
IPC分类号： H01L29/73 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/337 , H01L29/205 , H01L29/45 , H01L29/737 , H01L29/808
CPC分类号： H01L29/66924 , H01L21/28575 , H01L29/452 , H01L29/66318 , H01L29/7371 , H01L29/808 , Y10S148/01 , Y10S148/065
摘要： An electrode structure of an electrode of a refractory metal or a silicide thereof on a layer of In.sub.x Ga.sub.1-x As (0
摘要翻译：在III-V族化合物半导体的基板上的In x Ga 1-x As（0

4. 发明授权

US4791471A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4791471A
公开(公告)日：1988-12-13
申请号：US158043
申请日：1988-02-16
申请人： Tsukasa Onodera , Haruo Kawata , Toshiro Futatsugi
发明人： Tsukasa Onodera , Haruo Kawata , Toshiro Futatsugi
IPC分类号： H01L27/06 , H01L29/04 , H01L29/20 , H01L29/812
CPC分类号： H01L29/812 , H01L27/0605 , H01L29/045 , H01L29/20
摘要： In a semiconductor integrated circuit device, a plurality of a field effect transistors are formed on a (110) crystal surface of a group III-V compound semiconductor substrate having a zinc blend type crystal structure.
摘要翻译：在半导体集成电路器件中，在具有锌掺杂型晶体结构的III-V族化合物半导体衬底的（110）晶体表面上形成多个场效应晶体管。

5. 发明授权

US06195292B1 Semiconductor memory with floating gate type FET 有权
标题翻译：具有浮栅型FET的半导体存储器
公开(公告)号：US06195292B1
公开(公告)日：2001-02-27
申请号：US09437142
申请日：1999-11-10
申请人： Tatsuya Usuki , Toshiro Futatsugi
发明人： Tatsuya Usuki , Toshiro Futatsugi
IPC分类号： G11C1604
CPC分类号： H01L29/7883 , G11C16/0416 , H01L29/42324 , H01L29/4966
摘要： A source region and a drain region are formed in a surface layer of a semiconductor substrate on both sides of a channel region defined in the surface layer. A tunneling insulating film is formed on the channel region, the tunneling insulating film having a thickness which allows carriers to tunnel therethrough. A floating gate electrode is formed on the tunneling insulating film, the floating gate electrode being disposed so as to overlap neither the source region nor the drain region as viewed along a substrate normal direction. A gate insulating film is formed over the channel region, covering the floating gate electrode. A control gate electrode is formed on the gate insulating film, the control gate electrode being disposed so as to become in contact with, or partially overlap, the source and drain regions as viewed along the substrate normal direction. Materials of the floating gate electrode and channel region are selected so that a Fermi level of the floating gate electrode is positioned in an energy band gap of the channel region when an external voltage is not applied between the channel region and the control gate electrode.
摘要翻译：源极区域和漏极区域形成在表面层中限定的沟道区域的两侧的半导体衬底的表面层中。隧道绝缘膜形成在沟道区上，隧道绝缘膜具有允许载流子穿过其的厚度。在隧道绝缘膜上形成浮栅电极，浮置栅电极沿着衬底法线方向设置成不与源极区域和漏极区域重叠。栅极绝缘膜形成在通道区域上，覆盖浮栅电极。控制栅电极形成在栅极绝缘膜上，控制栅电极设置成沿着衬底法线方向与源区和漏区接触或部分重叠。选择浮栅电极和沟道区的材料，使得当沟道区和控制栅电极之间没有施加外部电压时，浮置栅电极的费米能级位于沟道区的能带隙中。

6. 发明授权

US5889288A Semiconductor quantum dot device 失效
标题翻译：半导体量子点器件
公开(公告)号：US5889288A
公开(公告)日：1999-03-30
申请号：US684917
申请日：1996-07-22
申请人： Toshiro Futatsugi
发明人： Toshiro Futatsugi
IPC分类号： H01L27/06 , H01L21/06 , H01L21/338 , H01L21/822 , H01L29/06 , H01L29/66 , H01L29/76 , H01L29/778 , H01L29/80 , H01L29/812 , H01L29/15 , H01L29/772
CPC分类号： B82Y10/00 , H01L27/0605 , H01L29/7613 , H01L29/7787
摘要： A semiconductor quantum dot device using a semiconductor quantum dot comprises a semiconductor quantum dot formed on a semiconductor wafer, a field effect transistor formed on said semiconductor wafer and comprising a gate electrode formed in a vicinity of said semiconductor quantum dot, and a coupling means to couple said gate electrode and said semiconductor quantum dot capacitively.
摘要翻译：使用半导体量子点的半导体量子点装置包括形成在半导体晶片上的半导体量子点，形成在所述半导体晶片上的场效应晶体管，并且包括形成在所述半导体量子点附近的栅电极和耦合装置，耦合所述栅电极和所述半导体量子点电容。

7. 发明授权

US5031005A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5031005A
公开(公告)日：1991-07-09
申请号：US111018
申请日：1987-10-21
申请人： Toshiro Futatsugi , Naoki Yokoyama , Kenichi Imamura
发明人： Toshiro Futatsugi , Naoki Yokoyama , Kenichi Imamura
IPC分类号： H01L29/08 , H01L29/205 , H01L29/737 , H01L33/00
CPC分类号： H01L29/7376 , B82Y10/00 , H01L29/0895 , H01L29/205 , H01L33/0004
摘要： A semiconductor device comprises stacked first through fifth semiconductor layers. The semiconductor device has an energy level condition of .vertline.Ec.sub.3 -Ec.sub.1 .vertline..apprxeq..vertline.Ev.sub.3 -Ev.sub.5 .vertline., where Ec.sub.3 is a resonant energy level of electrons in a conduction band of the third layer and Ev.sub.3 is a resonant energy level of holes in a valence band thereof, and Ec.sub.1 is an energy level of a conduction band of the first layer and Ev.sub.5 is an energy level of a valence band of the fifth layer.
摘要翻译：半导体器件包括堆叠的第一至第五半导体层。半导体器件具有| Ec3-Ec1 | APPROX | Ev3-Ev5|的能级条件，其中Ec3是第三层导带中的电子的共振能级，Ev3是化合价中的空穴的共振能级并且Ec1是第一层的导带的能级，Ev5是第五层的价带的能级。

8. 发明授权

US08013379B2 Semiconductor variable capacitor and method of manufacturing the same 有权
标题翻译：半导体可变电容器及其制造方法
公开(公告)号：US08013379B2
公开(公告)日：2011-09-06
申请号：US12055747
申请日：2008-03-26
申请人： Toshiro Futatsugi
发明人： Toshiro Futatsugi
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/93 , H01L29/66075
摘要： The semiconductor variable capacitor includes a capacitor including an n-well 16 formed in a first region of a semiconductor substrate 10, an insulating film 18 formed over the semiconductor substrate 10 and a gate electrode 20n formed above the n-well 16 with the insulating film 18 interposed therebetween; and a p-well 14 of a second conduction type formed in a second region adjacent to the first region of the semiconductor substrate 10. The gate electrode 20n has an end which is extended to the second region and formed above the p-well 14 with the insulating film 18 interposed therebetween.
摘要翻译：半导体可变电容器包括电容器，其包括形成在半导体衬底10的第一区域中的n阱16，形成在半导体衬底10上的绝缘膜18和形成在n阱16上方的栅电极20n，绝缘膜 18; 以及形成在与半导体衬底10的第一区域相邻的第二区域中的第二导电类型的p阱14.栅电极20n具有延伸到第二区域并在p阱14上方形成的端部，绝缘膜18插入其间。

9. 发明申请

US20050221556A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050221556A1
公开(公告)日：2005-10-06
申请号：US11099699
申请日：2005-04-06
申请人： Toshiro Futatsugi , Naoto Horiguchi , Ken-ichi Okabe , Kenichi Hikazutani
发明人： Toshiro Futatsugi , Naoto Horiguchi , Ken-ichi Okabe , Kenichi Hikazutani
IPC分类号： H01L27/04 , H01L21/02 , H01L21/316 , H01L21/822 , H01L21/8234 , H01L21/8242 , H01L27/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L28/40 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L27/0629 , H01L29/94
摘要： A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.
摘要翻译：一种制造半导体器件的方法，包括：通过以第一剂量注入杂质，在半导体衬底的第一区域中形成第一杂质扩散区域作为电容器的下电极; 通过以第二剂量注入杂质，在半导体衬底的端部的第二区域中形成第二杂质扩散区; 并通过热氧化法形成在第一杂质扩散区上具有第一厚度的电容器绝缘膜，并形成第二厚度比第二区域厚的第二厚度的氧化膜。

10. 发明授权

US06480420B2 Semiconductor memory device having source areas of memory cells supplied with a common voltage 有权
标题翻译：具有提供有公共电压的存储单元的源极区域的半导体存储器件
公开(公告)号：US06480420B2
公开(公告)日：2002-11-12
申请号：US09818652
申请日：2001-03-28
申请人： Toshiro Futatsugi
发明人： Toshiro Futatsugi
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/30
摘要： A semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, where each of the memory cells includes a source area formed adjacent to a channel area in the semiconductor substrate; a drain area formed opposite the source area with the channel area therebetween in the semiconductor substrate, the drain area being connected to one of the bit lines; a tunnel insulating film formed on the channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon; a floating gate formed on the tunnel insulating film so as to overlap neither the source area nor the drain area; a gate insulating film formed on the floating gate so as to cover the floating gate; and a control gate formed on the gate insulating film so as to partially overlap both of the source area and the drain area, the control gate being connected to one of the word lines. In the semiconductor memory device, the source areas of the memory cells are connected to each other so that a common voltage is supplied to each of the source areas.
摘要翻译：一种半导体存储器件，具有形成在半导体衬底上的多个存储单元，字线和位线，其中每个存储单元包括与半导体衬底中的沟道区相邻形成的源区; 在所述半导体衬底中与所述源极区域相对地形成有沟槽区域的漏极区域，所述漏极区域连接到所述位线之一; 形成在通道区域上的隧道绝缘膜，所述隧道绝缘膜具有用于载体通过隧道现象穿过的适当厚度; 在所述隧道绝缘膜上形成的浮栅，以便不与所述源极区域和所述漏极区域重叠; 形成在所述浮动栅极上以覆盖所述浮动栅极的栅极绝缘膜; 以及形成在所述栅极绝缘膜上以便部分地重叠所述源极区域和所述漏极区域的控制栅极，所述控制栅极连接到所述字线之一。在半导体存储器件中，存储单元的源极区域彼此连接，从而向每个源极区域提供公共电压。

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