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1. 发明授权

US5965939A Semiconductor device and a method of manufacture 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5965939A
公开(公告)日：1999-10-12
申请号：US838044
申请日：1997-04-22
申请人： Kyeong-tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
发明人： Kyeong-tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
IPC分类号： H01L21/3205 , H01L21/3105 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48
CPC分类号： H01L27/10808 , H01L21/31056 , H01L21/76819 , H01L27/105 , Y10S438/926
摘要： A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.
摘要翻译：提供一种半导体器件，其具有闭合台阶部分和包括在全局台阶部分上具有平坦化表面的绝缘层的全局阶跃部分。通过在全局台阶部分上形成绝缘层，然后通过光刻工艺进行图案化，形成虚拟图案。在形成用于补偿全局台阶部分之间和闭合台阶部分与全局台阶部分之间的步骤的虚拟图案之后，在封闭台阶部分和全局台阶部分上形成BPSG层，然后BPSG层被热封，处理以使其回流。作为具有平坦化表面的绝缘中间层的BPSG层。改进的平面化减少了随后的金属化处理中的开槽和不连续的发生，从而提高了半导体器件的产量和电特性。

2. 发明授权

US5488007A Method of manufacture of a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5488007A
公开(公告)日：1996-01-30
申请号：US42490
申请日：1993-04-16
申请人： Kyeong-Tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
发明人： Kyeong-Tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
IPC分类号： H01L21/3205 , H01L21/3105 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L21/00
CPC分类号： H01L27/10808 , H01L21/31056 , H01L21/76819 , H01L27/105 , Y10S438/926
摘要： A method for manufacturing a semiconductor device having a closed step portion and a global step portion including an insulating layer is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.
摘要翻译：提供了一种制造具有封闭台阶部分和包括绝缘层的全局台阶部分的半导体器件的方法。通过在全局台阶部分上形成绝缘层，然后通过光刻工艺进行图案化，形成虚拟图案。在形成用于补偿全局台阶部分之间和闭合台阶部分与全局台阶部分之间的步骤的虚拟图案之后，在封闭台阶部分和全局台阶部分上形成BPSG层，然后BPSG层被热封，处理以使其回流。作为具有平坦化表面的绝缘中间层的BPSG层。改进的平面化减少了随后的金属化处理中的开槽和不连续的发生，从而提高了半导体器件的产量和电特性。

3. 发明授权

US5502336A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5502336A
公开(公告)日：1996-03-26
申请号：US209475
申请日：1994-03-14
申请人： Won-mo Park , Jung-hyun Shin , Young-hun Park
发明人： Won-mo Park , Jung-hyun Shin , Young-hun Park
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L29/78
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , Y10S438/978
摘要： A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.
摘要翻译：公开了一种高度集成的半导体器件及其制造方法。该器件具有自对准的接触结构，用于在形成自对准的埋入接触孔时增加接触余量。为了形成自对准埋入接触孔，对栅电极的上部的氧化膜进行倒角处理。因此，可以在不改善步骤的情况下形成自对准的接触孔，结果，可以减小电池与电池的周边部分之间的步骤。

4. 发明授权

US5591670A Method of manufacturing a semiconductor device having self aligned contact hole 失效
标题翻译：制造具有自对准接触孔的半导体器件的方法
公开(公告)号：US5591670A
公开(公告)日：1997-01-07
申请号：US465103
申请日：1995-06-05
申请人： Won-mo Park , Jung-hyun Shin , Young-hun Park
发明人： Won-mo Park , Jung-hyun Shin , Young-hun Park
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L29/78 , H01L21/44
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , Y10S438/978
摘要： A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.
摘要翻译：公开了一种高度集成的半导体器件及其制造方法。该器件具有自对准的接触结构，用于在形成自对准的埋入接触孔时增加接触余量。为了形成自对准埋入接触孔，对栅电极的上部的氧化膜进行倒角处理。因此，可以在不改善步骤的情况下形成自对准的接触孔，结果，可以减小电池与电池的周边部分之间的步骤。

5. 发明申请

US20100120212A1 Method of forming capacitor of semiconductor memory device 有权
标题翻译：形成半导体存储器件电容器的方法
公开(公告)号：US20100120212A1
公开(公告)日：2010-05-13
申请号：US12591072
申请日：2009-11-06
申请人： Dong-kwan Yang , Seong-ho Kim , Won-mo Park , Gil-sub Kim
发明人： Dong-kwan Yang , Seong-ho Kim , Won-mo Park , Gil-sub Kim
IPC分类号： H01L21/8239 , H01L21/02
CPC分类号： H01L27/10817 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L27/10855
摘要： A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.
摘要翻译：形成半导体存储器件的方法包括顺序地形成蚀刻停止层，然后形成模具层，形成多个线状支撑结构，以及填充模具层上的支撑结构之间的间隙的第一牺牲层，依次形成多个线形的第一掩模图案，第二牺牲层，然后在支撑结构上和第一牺牲层上的第二掩模图案，使用第一掩模图案去除第二牺牲层，第一牺牲层和模具层，第二掩模图案和支撑结构作为掩模，去除第一掩模图案和第二掩模图案，用导电材料填充存储节点电极孔并蚀刻导电材料以暴露支撑结构，以及去除第一牺牲层和模具层，以形成由支撑结构支撑的柱状存储节点电极。

6. 发明授权

US5700709A Method for manufacturing a capacitor for a semiconductor device 失效
标题翻译：半导体装置用电容器的制造方法
公开(公告)号：US5700709A
公开(公告)日：1997-12-23
申请号：US547901
申请日：1995-10-25
申请人： Won-mo Park , Jong-jin Lee
发明人： Won-mo Park , Jong-jin Lee
IPC分类号： H01L27/04 , H01L21/306 , H01L21/3065 , H01L21/308 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S148/014
摘要： A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.
摘要翻译：一种半导体器件用电容器的制造方法，其特征在于，包括以下步骤：在半导体基板上形成第一导电层，通过图案化第一导电层形成第一图案，在第二导电层上依次形成第二导电层和第一材料层通过各向异性蚀刻第一材料层在第二导电层的侧壁上形成间隔物，通过使用间隔物作为蚀刻掩模部分蚀刻第二导电层和第一图案来形成第二图案在所得结构的整个表面上形成第三导电层，通过各向异性蚀刻第三导电层形成圆柱形的存储电极，并且去除间隔物。

7. 发明申请

US20120231619A1 METHOD OF FABRICATING AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 有权
标题翻译：使用该方法制造和半导体存储器件的方法
公开(公告)号：US20120231619A1
公开(公告)日：2012-09-13
申请号：US13414262
申请日：2012-03-07
申请人： Won-mo Park , Min-wk Hwang , Hyun-chul Kim
发明人： Won-mo Park , Min-wk Hwang , Hyun-chul Kim
IPC分类号： H01L21/283
CPC分类号： H01L21/76885 , G11C5/04 , G11C5/06 , H01L27/10894 , H01L27/10897
摘要： A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.
摘要翻译：一种制造半导体存储器件的方法包括制备半导体衬底，该半导体衬底被划分为单元阵列区域和与该单元阵列区域相邻的核心和外围区域。信号线可以形成在单元区域的下层中。可以在下层上形成绝缘层。连接到单元区域信号线的信号线可以形成在周边区域的绝缘层上。可以在绝缘层和芯和外围信号线上形成覆盖层。可以蚀刻覆盖层以暴露电池阵列区域的下层，并且可以在下层和芯部和外围区域上形成蚀刻停止。

8. 发明授权

US5443993A Method for manufacturing a capacitor for a semiconductor device 失效
标题翻译：半导体装置用电容器的制造方法
公开(公告)号：US5443993A
公开(公告)日：1995-08-22
申请号：US347246
申请日：1994-11-23
申请人： Won-mo Park , Jong-jin Lee
发明人： Won-mo Park , Jong-jin Lee
IPC分类号： H01L27/04 , H01L21/306 , H01L21/3065 , H01L21/308 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S148/014
摘要： A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.
摘要翻译：一种半导体器件用电容器的制造方法，其特征在于，包括以下步骤：在半导体基板上形成第一导电层，通过图案化第一导电层形成第一图案，在第二导电层上依次形成第二导电层和第一材料层通过各向异性蚀刻第一材料层在第二导电层的侧壁上形成间隔物，通过使用间隔物作为蚀刻掩模部分蚀刻第二导电层和第一图案来形成第二图案在所得结构的整个表面上形成第三导电层，通过各向异性蚀刻第三导电层形成圆柱形的存储电极，并且去除间隔物。

9. 发明授权

US08883622B2 Method of fabricating and semiconductor memory device using the same 有权
标题翻译：制造方法及使用其的半导体存储器件
公开(公告)号：US08883622B2
公开(公告)日：2014-11-11
申请号：US13414262
申请日：2012-03-07
申请人： Won-mo Park , Min-wk Hwang , Hyun-chul Kim
发明人： Won-mo Park , Min-wk Hwang , Hyun-chul Kim
IPC分类号： H01L21/283 , H01L27/108 , G11C5/04 , H01L21/768 , G11C5/06
CPC分类号： H01L21/76885 , G11C5/04 , G11C5/06 , H01L27/10894 , H01L27/10897
摘要： A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.
摘要翻译：一种制造半导体存储器件的方法包括制备半导体衬底，该半导体衬底被划分为单元阵列区域和与该单元阵列区域相邻的核心和外围区域。信号线可以形成在单元区域的下层中。可以在下层上形成绝缘层。连接到单元区域信号线的信号线可以形成在周边区域的绝缘层上。可以在绝缘层和芯和外围信号线上形成覆盖层。可以蚀刻覆盖层以暴露电池阵列区域的下层，并且可以在下层和芯部和外围区域上形成蚀刻停止。

10. 发明授权

US08043925B2 Method of forming capacitor of semiconductor memory device 有权
标题翻译：形成半导体存储器件电容器的方法
公开(公告)号：US08043925B2
公开(公告)日：2011-10-25
申请号：US12591072
申请日：2009-11-06
申请人： Dong-kwan Yang , Seong-ho Kim , Won-mo Park , Gil-sub Kim
发明人： Dong-kwan Yang , Seong-ho Kim , Won-mo Park , Gil-sub Kim
IPC分类号： H01L21/20
CPC分类号： H01L27/10817 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L27/10855
摘要： A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.
摘要翻译：形成半导体存储器件的方法包括顺序地形成蚀刻停止层，然后形成模具层，形成多个线状支撑结构，以及填充模具层上的支撑结构之间的间隙的第一牺牲层，依次形成多个线形的第一掩模图案，第二牺牲层，然后在支撑结构上和第一牺牲层上的第二掩模图案，使用第一掩模图案去除第二牺牲层，第一牺牲层和模具层，第二掩模图案和支撑结构作为掩模，去除第一掩模图案和第二掩模图案，用导电材料填充存储节点电极孔并蚀刻导电材料以暴露支撑结构，以及去除第一牺牲层和模具层，以形成由支撑结构支撑的柱状存储节点电极。

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