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1. 发明授权

US5965939A Semiconductor device and a method of manufacture 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5965939A
公开(公告)日：1999-10-12
申请号：US838044
申请日：1997-04-22
申请人： Kyeong-tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
发明人： Kyeong-tae Kim , Yun-seung Shin , Young-hun Park , Won-mo Park , Ji-hong Ahn
IPC分类号： H01L21/3205 , H01L21/3105 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48
CPC分类号： H01L27/10808 , H01L21/31056 , H01L21/76819 , H01L27/105 , Y10S438/926
摘要： A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.
摘要翻译：提供一种半导体器件，其具有闭合台阶部分和包括在全局台阶部分上具有平坦化表面的绝缘层的全局阶跃部分。通过在全局台阶部分上形成绝缘层，然后通过光刻工艺进行图案化，形成虚拟图案。在形成用于补偿全局台阶部分之间和闭合台阶部分与全局台阶部分之间的步骤的虚拟图案之后，在封闭台阶部分和全局台阶部分上形成BPSG层，然后BPSG层被热封，处理以使其回流。作为具有平坦化表面的绝缘中间层的BPSG层。改进的平面化减少了随后的金属化处理中的开槽和不连续的发生，从而提高了半导体器件的产量和电特性。

2. 发明授权

US5330614A Manufacturing method of a capacitor having a storage electrode whose sidewall is positively inclined with respect to the horizontal surface 失效
标题翻译：具有其侧壁相对于水平面正向倾斜的存储电极的电容器的制造方法
公开(公告)号：US5330614A
公开(公告)日：1994-07-19
申请号：US917182
申请日：1992-07-22
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/04 , H01L21/033 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/306
CPC分类号： H01L27/10852 , H01L21/0337 , H01L27/10817 , Y10S438/947
摘要： Disclosed are a semiconductor memory device and method for manufacturing the same. The method includes a process for manufacturing a capacitor performed by the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern composed of a 1st first-material layer on the first conductive layer, forming a first sidewall spacer composed of 1st second-material layer on the resultant structure, and etching the material layer under the first sidewall spacer, using the first sidewall spacer as an etch-mask. The semiconductor memory device thus manufactured can be highly integrated and is highly reliable.
摘要翻译：公开了半导体存储器件及其制造方法。该方法包括一种制造电容器的方法，该方法包括以下步骤：在半导体衬底上形成第一导电层，在第一导电层上形成由第一第一材料层构成的第一图案，形成第一侧墙，第二材料层，并且使用第一侧壁间隔物作为蚀刻掩模来蚀刻第一侧壁间隔物下方的材料层。如此制造的半导体存储器件可以高度集成并且是高度可靠的。

3. 发明授权

US5164881A Highly integrated semiconductor memory device and the fabrication method thereof 失效
标题翻译：高集成半导体存储器件及其制造方法
公开(公告)号：US5164881A
公开(公告)日：1992-11-17
申请号：US814469
申请日：1991-12-30
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10817 , Y10S438/947
摘要： In a highly integrated semiconductor memory device provided with memory cells in matrix form on a semiconductor substrate, each memory cell includes a transistor and a capacitor. The cell capacitor includes a storage electrode in contact with a source region of the transistor. This storage electrode has a plurality of irregularly shaped quasi-cylindrical holes formed therein at random locations. A dielectric film is coated on the whole surface of the storage electrode. Thus, storage electrodes having a large cell capacitance suitable for DRAM cells of highly integrated circuits can be achieved.
摘要翻译：在半导体衬底上以矩阵形式提供存储单元的高度集成的半导体存储器件中，每个存储单元包括晶体管和电容器。电池电容器包括与晶体管的源极区域接触的存储电极。该存储电极在随机位置形成有多个不规则形状的准圆柱形孔。电介质膜被涂覆在存储电极的整个表面上。因此，可以实现具有适合于高集成电路的DRAM单元的大电池电容的存储电极。

4. 发明授权

US5158905A Method for manufacturing a semiconductor device with villus-type capacitor 失效
标题翻译：用VILLUS型电容器制造半导体器件的方法
公开(公告)号：US5158905A
公开(公告)日：1992-10-27
申请号：US715796
申请日：1991-06-14
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/04 , H01L21/02 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L21/32139 , H01L27/10817 , H01L28/92
摘要： A method for manufacturing a villus-type capacitor of a semiconductor memory device formed by stacking a storage electrode, a dielectric film and a plate electrode on a semiconductor substrate further comprising the steps of forming a first conductive layer by depositing a conductive material on the semiconductor substrate; covering the first conductive layer with a second material having grains of a first material; selectively removing the second material using the grains of the first material as a mask; etching a predetermined portion of the first conductive layer using a grain pattern formed by removing the second material as a mask; removing the grain pattern; completing the formation of a storage electrode by defining into each unit cell the villus-formed first conductive layers on the surface of the device utillizing an etching process; forming the dielectric film over the surface of the storage electrode; and forming the plate electrode by depositing a second conductive layer over the dielectric film. The pillar-shaped storage electrode having dimensions below design rules and a buried bit line extend the capacitor's surface, resulting in an effective increase of capacitive area, and a corresponding increase in the cell capacitance.
摘要翻译：一种制造半导体存储器件的绒毛型电容器的方法，该半导体存储器件通过在半导体衬底上堆叠存储电极，电介质膜和平板电极而形成，还包括以下步骤：通过在半导体上沉积导电材料形成第一导电层基质; 用具有第一材料颗粒的第二材料覆盖第一导电层; 使用第一材料的晶粒作为掩模选择性地去除第二材料; 使用通过除去第二材料作为掩模形成的颗粒图案来蚀刻第一导电层的预定部分; 去除纹理图案; 通过在每个单元电池中限定形成蚀刻工艺的器件表面上的绒毛形成的第一导电层来完成存储电极的形成; 在所述存储电极的表面上形成所述电介质膜; 以及通过在所述电介质膜上沉积第二导电层来形成所述平板电极。具有尺寸低于设计规则的柱状存储电极和掩埋位线延伸电容器的表面，导致电容面积的有效增加和电池电容的相应增加。

5. 发明授权

US5134086A Method for manufacturing capacitor of highly integrated semiconductor memory device 失效
标题翻译：高度集成半导体存储器件的电容器制造方法
公开(公告)号：US5134086A
公开(公告)日：1992-07-28
申请号：US784534
申请日：1991-10-29
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92 , H01L28/84 , Y10S438/964
摘要： A method for manufacturing a capacitor of a highly integrated semiconductor memory device including a plurality of memory cells, each of which has a transistor and a capacitor. The method comprises the steps of forming an insulating layer for insulating the transistor, forming a contact hole to electrically connect to a source region by etching the insulating layer, sequentially forming a first polycrystalline silicon layer, an oxide layer, and a second polycrystalline silicon layer consisting of grains, exposing the second polycrystalline silicon layer to an oxide etchant, partially etching the oxide layer by the oxide etchant penetrating along the peripheries of the grains, anistropically etching the whole second polycrystalline silicon layer and, at the same time, the partial first polycrystalline silicon layer also, using the oxide layer being unaffected by the oxide etchant, as a mask, removing the oxide layer, forming a storage electrode by defining into cell units the first polycrystalline silicon layer, sequentially forming a dielectric film and a plate electrode formed of a third polycrystalline silicon layer over the resultant structure. Thus, the physical properties of the material itself is used without any specific conditions and unrestricted by limitation of minimum feature size. Furthermore, the process is greatly simplified and the effective capacitance of the cell capacitor is easily extended.
摘要翻译：一种制造具有多个存储单元的高度集成的半导体存储器件的电容器的方法，每个存储单元都具有晶体管和电容器。该方法包括以下步骤：形成用于使晶体管绝缘的绝缘层，通过蚀刻绝缘层形成接触孔以与源极区电连接，顺序地形成第一多晶硅层，氧化物层和第二多晶硅层由晶粒组成，将第二多晶硅层暴露于氧化物蚀刻剂，通过沿着晶粒周边渗透的氧化物蚀刻剂部分地蚀刻氧化物层，从根本上蚀刻整个第二多晶硅层，同时蚀刻部分第一多晶硅层多晶硅层，也可以使用不受氧化物蚀刻剂影响的氧化物层作为掩模，去除氧化物层，通过将电极单元限定为单电池单元形成第一多晶硅层，依次形成电介质膜和形成的平板电极在所得结构上的第三多晶硅层。因此，材料本身的物理性质在没有任何特定条件的情况下使用，并且不受限于最小特征尺寸的限制。此外，该过程被大大简化，并且容易延长单元电容器的有效电容。

6. 发明授权

US5386382A Semiconductor memory device and a manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5386382A
公开(公告)日：1995-01-31
申请号：US129369
申请日：1993-09-30
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L23/485 , H01L27/10 , H01L27/108 , H01L27/02
CPC分类号： H01L27/10852 , H01L21/768 , H01L23/485 , H01L27/10817 , H01L2924/0002
摘要： A semiconductor memory device includes a cell array region and a peripheral circuit region, wherein a channel is formed to surround the cell array region, on a border region between the cell array region and peripheral circuit region. Also, a method for the semiconductor memory device is provided. Therefore, the conventional problem of degraded reliability of the conductive layer due to the step between the cell array region and peripheral circuit region, can be prevented. At the same time, the surface planarization of the peripheral circuit region can be attained.
摘要翻译：半导体存储器件包括单元阵列区域和外围电路区域，其中在单元阵列区域和外围电路区域之间的边界区域上形成有围绕单元阵列区域的沟道。此外，提供了一种用于半导体存储器件的方法。因此，可以防止由于电池阵列区域和外围电路区域之间的步骤导致的导电层的可靠性降低的常规问题。同时，可以实现外围电路区域的表面平坦化。

7. 发明授权

US5284787A Method of making a semiconductor memory device having improved electrical characteristics 失效
标题翻译：制造具有改善的电特性的半导体存储器件的方法
公开(公告)号：US5284787A
公开(公告)日：1994-02-08
申请号：US815247
申请日：1991-12-31
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A semiconductor memory device and the method therefor is disclosed, in which memory cells having a transistor that has a source, a drain and a gate electrode, and a capacitor that has a storage electrode electrically connected to the source of the transistor, a dielectric layer and a plate electrode are formed on a semiconductor substrate in an orderly shape. In the memory cell, a covering layer is formed over the entire semiconductor region, except for an area defined to form the storage electrode, so as to be both insulated from the lower structure and the storage electrode. Accordingly, not only is prevented the phenomenon that data stored in a cell capacitor is destroyed by the residue of a polycrystal silicon layer, but also the surface thereof can be flattened in advance, limited only by the thickness of the polycrystal silicon layer.
摘要翻译：公开了一种半导体存储器件及其方法，其中具有源极，漏极和栅电极的晶体管的存储单元和具有与晶体管的源极电连接的存储电极的电容器，介电层并且在半导体基板上形成有序形状的平板电极。在存储单元中，除了形成存储电极的区域之外，在整个半导体区域上形成覆盖层，以便与下部结构和存储电极绝缘。因此，不仅防止存储在电池电容器中的数据被多晶硅层的残留物破坏，而且其表面也可以预先平坦化，而仅受多晶硅层的厚度的限制。

8. 发明授权

US5274258A High density semiconductor memory device (MBC cell) 失效
标题翻译：高密度半导体存储器件（MBC单元）
公开(公告)号：US5274258A
公开(公告)日：1993-12-28
申请号：US715913
申请日：1991-06-14
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108 , H01L27/02
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92
摘要： A high-density semiconductor memory device and its manufacturing method are disclosed. The device has a plurality of memory cells, each consisting of one transistor and one capacitor on a substrate in a matrix form. The capacitor, in contact with the source region of the transistor, consists of a storage electrode having a hollow cylindrical electrode with a wall of predetermined thickness, and a column electrode surrounded by the cylindrical electrode. The capacitor further comprises a plurality of bars, a base plate electrode connecting the cylindrical and column electrodes to each other, a dielectric layer coating the whole surface of the storage electrode, and a plate electrode formed on top of the dielectric layer. According to this invention, a greater capacitance may be obtained while avoiding current leakage and the disparity of cell capacitance problems involved with a conventional stack-type capacitor having a ringed structure.
摘要翻译：公开了一种高密度半导体存储器件及其制造方法。该器件具有多个存储单元，每个存储单元由矩阵形式的基板上的一个晶体管和一个电容器构成。与晶体管的源极区域接触的电容器由具有预定厚度的壁的中空圆柱形电极的存储电极和被圆柱形电极包围的列电极组成。电容器还包括多个条，将圆柱和柱电极彼此连接的基板电极，覆盖存储电极的整个表面的电介质层和形成在电介质层的顶部上的平板电极。根据本发明，可以获得更大的电容，同时避免电流泄漏以及与具有环形结构的常规堆叠型电容器相关的电池电容问题的不均匀性。

9. 发明授权

US5358888A Method for manufacturing a capacitor of an integrated semiconductor device having increased surface area 失效
标题翻译：具有增加的表面积的集成半导体器件的电容器的制造方法
公开(公告)号：US5358888A
公开(公告)日：1994-10-25
申请号：US992905
申请日：1992-12-18
申请人： Ji-hong Ahn , Young-woo Seo
发明人： Ji-hong Ahn , Young-woo Seo
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： A method for manufacturing a capacitor of a highly integrated semiconductor memory device includes the steps of forming a conductive layer on the whole surface of a semiconductor substrate, forming a first material layer on the whole surface of the conductive layer, forming a polysilicon layer having hemispherical grains on the whole surface of the first material layer, forming a first material layer pattern by performing an etching on the first material layer, using the polysilicon layer as an etch-mask, partially removing the conductive layer by anisotropically etching the conductive layer, using the first material layer pattern as an etch-mask, defining the conductive layer into an individual unit cell, and removing the first material layer pattern. Since greater cell capacitance can be secured by a simple process, this method can be adopted to manufacturing semiconductor memory devices having packing densities up to 64 Mb and 256 Mb.
摘要翻译：一种高度集成的半导体存储器件的电容器的制造方法，其特征在于，在半导体基板的整个表面形成导电层，在导体层的整个表面形成第一材料层，形成半导体层晶粒在第一材料层的整个表面上，通过使用多晶硅层作为蚀刻掩模，在第一材料层上进行蚀刻形成第一材料层图案，通过各向异性蚀刻导电层来部分地去除导电层，使用所述第一材料层图案作为蚀刻掩模，将所述导电层限定为单个单元电池，以及去除所述第一材料层图案。由于可以通过简单的工艺来确保更大的电池电容，因此可以采用该方法制造具有高达64Mb和256Mb的封装密度的半导体存储器件。

10. 发明授权

US5279983A Method of making a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US5279983A
公开(公告)日：1994-01-18
申请号：US906376
申请日：1992-06-30
申请人： Ji-hong Ahn
发明人： Ji-hong Ahn
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L23/485 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L21/768 , H01L23/485 , H01L27/10817 , H01L2924/0002
摘要： A semiconductor memory device includes a cell array region and a peripheral circuit region, wherein a channel is formed to surround the cell array region, on a border region between the cell array region and peripheral circuit region. Also, a method for the semiconductor memory device is provided. Therefore, the conventional problem of degraded reliability of the conductive layer due to the step between the cell array region and peripheral circuit region, can be prevented. At the same time, the surface planarization of the peripheral circuit region can be attained.
摘要翻译：半导体存储器件包括单元阵列区域和外围电路区域，其中在单元阵列区域和外围电路区域之间的边界区域上形成有围绕单元阵列区域的沟道。此外，提供了一种用于半导体存储器件的方法。因此，可以防止由于电池阵列区域和外围电路区域之间的步骤导致的导电层的可靠性降低的常规问题。同时，可以实现外围电路区域的表面平坦化。

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