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1. 发明授权

US5070179A Water-soluble copolymerized polyester resin composition 失效
标题翻译：水溶性共聚聚酯树脂组合物
公开(公告)号：US5070179A
公开(公告)日：1991-12-03
申请号：US653963
申请日：1991-02-12
申请人： Kwang T. Kim , Tae H. Kim , Young S. Kim
发明人： Kwang T. Kim , Tae H. Kim , Young S. Kim
IPC分类号： C08G63/66 , C08G63/181 , C08G63/46 , C08G63/672 , C08G63/68 , C08G63/688 , C08G63/695 , C08L67/00 , C08L67/02 , C09D167/02
CPC分类号： C08G63/672 , C08G63/68
摘要： The present invention relates to water-soluble copolymerized polyester resin suitable to produce a polyester film having a good adhesion and surface properties.That is, the composition of the present invention comprise 50.about.85 mol % of aromatic dicarbonic acid, 0.5.about.25 mol % of aromatic dicarbonic acid containing sulfonic acid alkali metallic base and 0.5.about.25 mol % of dicarbonic acid containing silane system represented by the following formula (I) in the total dicorbonic acid components, wherein the glycol components contained in the composition comprising more than 60 mol % of aliphatic or alicyclic glycol and 1.about.40 mol % of diethylene glycol or triethylene glycol. ##STR1## wherein R.sub.1 is aliphatic hydrocarbon group of 1 to 15 carbon atoms, R.sub.2 is aliphatic hydrocarbon group of 1 to 4 carbon atoms.
摘要翻译：本发明涉及适于生产具有良好粘附性和表面性能的聚酯薄膜的水溶性共聚聚酯树脂。也就是说，本发明的组合物包含50％的芳族二羧酸85摩尔％，含有20摩尔％的含有磺酸碱金属碱的芳族二碳酸的0.5分子和含有25摩尔％的含二羧酸的硅烷体系的0.5分子在总二氯碳酸组分中的下式（I）表示，其中所述组合物中所含的二醇组分包含超过60摩尔％的脂族或脂环族二醇和1分子量40摩尔％的二甘醇或三甘醇。（I）其中R 1为1至15个碳原子的脂族烃基，R 2为1至4个碳原子的脂族烃基。

2. 发明授权

US5382651A Method for the preparation of polyester for a film 失效
标题翻译：薄膜聚酯的制备方法
公开(公告)号：US5382651A
公开(公告)日：1995-01-17
申请号：US107067
申请日：1993-08-17
申请人： Kwang T. Kim , Tae H. Kim , Seung B. Jun
发明人： Kwang T. Kim , Tae H. Kim , Seung B. Jun
IPC分类号： C08G63/78 , C08K3/36
CPC分类号： C08G63/78 , C08K3/36
摘要： A method for the production of polyester suitable to be molded into a film with excellent surface properties.The method comprises passing dispersion-in-water type silica sol with pH 8 to 11 including sodium oxide as a stabilizer and silica particles with average diameters 0.01 to 0.3 .mu.m through a column of cation exchange resin having the following formula 1 and the strong basic anion exchange having the following formula 2, in sequence to adjust the pH value to 2 to 4, adding an hydrogen bonding agent and ethylene glycol thereto, heating the resultant silica sol under a reduced pressure to remove water, so as to obtain dispersion-in-ethylene glycol type silica sol, and adding 0.01 to 5% by weight of the dispersion-in-ethylene glycol type silica sol, as based on the weight of polyester to be produced, at any step during the ester interchange reaction. ##STR1##
摘要翻译：一种生产聚酯的方法，适用于模塑成具有优异表面性能的膜。该方法包括通过具有下列通式1的阳离子交换树脂柱和通式为1的阳离子交换树脂柱，通过含有pH8〜11的水分散型二氧化硅溶胶，包括氧化钠作为稳定剂，平均粒径为0.01〜0.3μm的二氧化硅粒子按照下式2的阴离子交换，将pH值调整为2〜4，向其中加入氢键合剂和乙二醇，在减压下加热得到的二氧化硅溶胶除去水，得到分散体 - 乙二醇型二氧化硅溶胶，并且在酯交换反应期间的任何步骤中，以所生产的聚酯的重量计，添加0.01-5重量％的乙二醇型二氧化硅溶胶分散体。（1）（2）

3. 发明授权

US08743628B2 Line driver circuits, methods, and apparatuses 有权
标题翻译：线路驱动器电路，方法和装置
公开(公告)号：US08743628B2
公开(公告)日：2014-06-03
申请号：US13204994
申请日：2011-08-08
申请人： Tae H. Kim , Howard C. Kirsch , Yu-Wen Huang , Mingshiang Wang , Todd A. Merritt
发明人： Tae H. Kim , Howard C. Kirsch , Yu-Wen Huang , Mingshiang Wang , Todd A. Merritt
IPC分类号： G11C7/00
CPC分类号： G11C11/4085 , G11C7/18 , G11C8/08
摘要： Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.
摘要翻译：描述的实施例涉及线路驱动器，例如用于在存储器阵列中提供减小的栅极感应漏极泄漏的线路驱动器。还公开了线路驱动器的相应的操作方法。

4. 发明授权

US08495537B1 Timing analysis of an array circuit cross section 失效
标题翻译：阵列电路截面的时序分析
公开(公告)号：US08495537B1
公开(公告)日：2013-07-23
申请号：US13349325
申请日：2012-01-12
申请人： Shyamkumar Thoziyoor , Tae H. Kim , Sang Y. Lee
发明人： Shyamkumar Thoziyoor , Tae H. Kim , Sang Y. Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.
摘要翻译：一种用于对阵列电路进行定时分析的方法，系统或计算机可用程序产品，包括在存储器中接收要定时的一组引脚，用数据处理器选择包括该组引脚的阵列电路的横截面，其中回溯是从所述一组引脚执行以识别一组总线组，每个总线组具有多个定时引脚，以及为第一总线组的分配引脚分配等于基于第一总线组的替代引脚的定时的定时阵列电路规律性。

5. 发明申请

US20090308649A1 Printed Circuit Board With Reduced Signal Distortion 有权
标题翻译：具有减少信号失真的印刷电路板
公开(公告)号：US20090308649A1
公开(公告)日：2009-12-17
申请号：US12140730
申请日：2008-06-17
申请人： Moises Cases , Tae H. Kim , Bhyrav M. Mutnury
发明人： Moises Cases , Tae H. Kim , Bhyrav M. Mutnury
IPC分类号： H05K1/11 , H05K3/00 , G06F17/50
CPC分类号： H05K1/0224 , H05K1/0225 , H05K1/0237 , H05K1/0253 , H05K3/0005 , H05K2201/09681 , Y10T29/49124
摘要： A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.
摘要翻译：具有降低的信号失真的印刷电路板，包括一层或多层不导电基底，在其上设置传导信号的导电路径，其特征在于至少部分地由印刷的层上的导电路径的取向引起的变形电路板和周期性图案化参考平面; 每个导电通路相对于在印刷电路板上传导信号的其它导电通路传导正交或对角地定向四十五度的信号; 所述周期性图案化参考平面包括具有以周期性重复图案布置的不连续性的导体，所述不连续性的图案相对于在所述印刷电路板上传导信号的导电路径以最佳角度定向在所述印刷电路板的层的表面上印刷电路板，可以减少信号的失真。

6. 发明授权

US07200053B2 Level shifter for low voltage operation 有权
标题翻译：电平移位器用于低电压工作
公开(公告)号：US07200053B2
公开(公告)日：2007-04-03
申请号：US10931587
申请日：2004-09-01
申请人： Tae H. Kim , Michael V. Cordoba , Howard C. Kirsch
发明人： Tae H. Kim , Michael V. Cordoba , Howard C. Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , G11C16/30 , H03K3/356113
摘要： A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.
摘要翻译：电压电平转换器提高晶体管的栅极电压，并增加栅极到源极电压，以允许在更宽的电源电压范围内工作。因此，电压电平转换器中的晶体管的P / N比被增加，并且节点的翻转的控制取决于栅极电压而不是P / N比。

7. 发明授权

US5503696A Method for fabricating a magnetic head 失效
标题翻译：磁头制造方法
公开(公告)号：US5503696A
公开(公告)日：1996-04-02
申请号：US234276
申请日：1994-04-28
申请人： Tae H. Kim
发明人： Tae H. Kim
IPC分类号： G11B5/127 , G11B5/133 , G11B5/147 , G11B5/187 , G11B5/23 , G11B5/235
CPC分类号： G11B5/232 , G11B5/1335 , G11B5/1878 , G11B5/235 , Y10T156/1062 , Y10T156/1069 , Y10T156/1075
摘要： A method for fabricating a magnetic head includes steps of stacking a magnetic layer on a ceramic substrate, coating an adhesive over the magnetic layer while rotating the substrate in a predetermined speed, forming a substrate block by stacking a plurality of substrates, and forming at least one pair of magnetic ferrite blocks by vertically and longitudinally slicing the substrate block. The adhesive is consistently coated on a gap formation plane of the magnetic ferrite block while being rotated by a predetermined speed, the pair of ferrite blocks are pressed to be bonded to each other, thereby completing the magnetic head.
摘要翻译：一种用于制造磁头的方法包括以下步骤：在陶瓷基片上层叠磁性层，同时以预定速度旋转衬底，在磁性层上涂覆粘合剂，通过堆叠多个衬底形成衬底块，至少形成一对磁性铁氧体块通过垂直和纵向地切割衬底块。粘合剂一直涂覆在磁性铁氧体块的间隙形成平面上同时以预定的速度旋转，一对铁氧体块被按压以彼此接合，从而完成磁头。

8. 外观设计

USD332837S Auxiliary vehicle brake light 失效
公开(公告)号：USD332837S
公开(公告)日：1993-01-26
申请号：US480505
申请日：1990-02-15
申请人： Tae H. Kim
设计人： Tae H. Kim

9. 发明申请

US20210212388A1 Tool and Method for Securing a Pocket Square 有权
公开(公告)号：US20210212388A1
公开(公告)日：2021-07-15
申请号：US16069786
申请日：2018-03-15
申请人： Tae H. Kim
发明人： Tae H. Kim
IPC分类号： A41B15/02 , A45F5/04
摘要： A pocket square tool comprises a pliable outer rod in a closed loop, having a substantially straight horizontal top edge and a curved U-shaped bottom edge, and a substantially straight pliable horizontal intermediate rod extending a horizontal distance between a left edge of the outer rod and a right edge of the outer rod and parallel to the top edge of the outer rod. The pocket square tool is adjustable in size. There are two intermediate rods parallel to each other. Other embodiments may have additional intermediate rods. The intermediate rods can be coupled to the outer rod or formed integral to it. Various methods of securing a pocket square use the tool.

10. 发明申请

US20130185685A1 TIMING ANALYSIS OF AN ARRAY CIRCUIT CROSS SECTION 失效
标题翻译：阵列电路交叉部分的时序分析
公开(公告)号：US20130185685A1
公开(公告)日：2013-07-18
申请号：US13349325
申请日：2012-01-12
申请人： Shyamkumar Thoziyoor , Tae H. Kim , Sang Y. Lee
发明人： Shyamkumar Thoziyoor , Tae H. Kim , Sang Y. Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.
摘要翻译：一种用于对阵列电路进行定时分析的方法，系统或计算机可用程序产品，包括在存储器中接收要定时的一组引脚，用数据处理器选择包括所述一组引脚的阵列电路的横截面，其中回溯是从所述一组引脚执行以识别一组总线组，每个总线组具有多个定时引脚，以及为第一总线组的分配引脚分配等于基于第一总线组的替代引脚的定时的定时阵列电路规律性。

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