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1. 发明申请

US20120126885A1 DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME 有权
标题翻译：双环4F2 DRAM CHC电池及其制造方法
公开(公告)号：US20120126885A1
公开(公告)日：2012-05-24
申请号：US12950797
申请日：2010-11-19
申请人： Werner Juengling , Howard C. Kirsch
发明人： Werner Juengling , Howard C. Kirsch
IPC分类号： H01L29/78 , H03K17/00 , H01L21/28
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L29/0847 , H01L29/1037 , H01L29/4236 , H01L29/66484 , H01L29/66787 , H01L29/7855
摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.
摘要翻译：提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。还包括制造和操作设备的方法。一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。

2. 发明申请

US20090237996A1 MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS 有权
标题翻译：具有挥发性和非易失性记忆体的记忆结构
公开(公告)号：US20090237996A1
公开(公告)日：2009-09-24
申请号：US12052300
申请日：2008-03-20
申请人： Howard C. Kirsch , Charles Ingalls , Werner Juengling
发明人： Howard C. Kirsch , Charles Ingalls , Werner Juengling
IPC分类号： G11C11/34 , H01L29/78
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译：提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分行的存储单元。

3. 发明申请

US20090129188A1 Devices and methods for a threshold voltage difference compensated sense amplifier 有权
标题翻译：阈值电压差补偿读出放大器的器件和方法
公开(公告)号：US20090129188A1
公开(公告)日：2009-05-21
申请号：US11986333
申请日：2007-11-20
申请人： Tae Kim , Howard C. Kirsch
发明人： Tae Kim , Howard C. Kirsch
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C7/062
摘要： Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.
摘要翻译：针对电压补偿的读出放大器描述实施例。一个这样的感测放大器包括分别耦合到一对晶体管的一对数字线节点。第一对开关适于将晶体管的栅极交叉耦合到相应的数字线节点，并且第二对开关适于将晶体管的栅极耦合到电压源。第一和第二对开关耦合到晶体管的相应栅极，独立于一对晶体管分别耦合到数字线节点。

4. 发明申请

US20080176378A1 MULTIPLE-DEPTH STI TRENCHES IN INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：集成电路制造中的多层深度STI
公开(公告)号：US20080176378A1
公开(公告)日：2008-07-24
申请号：US12057643
申请日：2008-03-28
申请人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译：集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

5. 发明授权

US07365384B2 Trench buried bit line memory devices and methods thereof 有权
标题翻译：沟槽掩埋位线存储器件及其方法
公开(公告)号：US07365384B2
公开(公告)日：2008-04-29
申请号：US11588748
申请日：2006-10-27
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
摘要翻译：存储器件包括大致平行于并沿着有源区域的相关带形成的隔离沟槽。导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

6. 发明授权

US07254074B2 Open digit line array architecture for a memory array 有权
公开(公告)号：US07254074B2
公开(公告)日：2007-08-07
申请号：US11074518
申请日：2005-03-07
申请人： Sei Seung Yoon , Charles L. Ingalls , David Pinney , Howard C. Kirsch
发明人： Sei Seung Yoon , Charles L. Ingalls , David Pinney , Howard C. Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

7. 发明授权

US06925019B2 Method and system for accelerating coupling of digital signals 有权
标题翻译：加速数字信号耦合的方法和系统
公开(公告)号：US06925019B2
公开(公告)日：2005-08-02
申请号：US10830888
申请日：2004-04-22
申请人： Howard C. Kirsch
发明人： Howard C. Kirsch
IPC分类号： G11C7/10 , G11C8/02 , G11C7/00
CPC分类号： G11C7/1096 , G11C7/1048 , G11C7/1078
摘要： A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an increase in the voltage of the I/O line above the precharge low voltage. The accelerate high circuit then drives the I/O line toward a high voltage, such as VCC. Similarly, an accelerate low circuit coupled to each of the I/O lines that has been precharged high detects a decrease in the voltage of the I/O line below the precharge high voltage. The accelerate low circuit then drives the I/O line to a low voltage, such as ground.
摘要翻译：用于通过存储器阵列的I / O线耦合读取数据信号和写入数据信号的系统和方法。预充电电路将交变信号线预充电到高和低预充电电压。连接到已经预充电的每个I / O线的加速高电平检测到I / O线的电压在预充电低电压之上的增加。然后，加速高电路将I / O线驱动到高电压，例如V CC CC。类似地，耦合到已经预充电的每个I / O线的加速低电平检测到I / O线的电压降低到预充电高电压以下。加速低电压然后将I / O线驱动到低电压，例如接地。

8. 发明授权

US06888769B2 Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage 有权
标题翻译：减少存取晶体管子阈值泄漏降低DRAM刷新功率的方法和电路
公开(公告)号：US06888769B2
公开(公告)日：2005-05-03
申请号：US10231626
申请日：2002-08-29
申请人： Howard C. Kirsch
发明人： Howard C. Kirsch
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4067 , G11C2211/4068
摘要： The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.
摘要翻译：通过将有效数字线偏置为轻微的正电压来降低DRAM的所需刷新率，以减少未被访问的存储器单元中的存取晶体管的次阈值电流泄漏。轻微的正电压由电压调节器电路提供，该电压调节器电路使用在阱中制造的一个或多个双极晶体管，其将双极晶体管与衬底的其余部分电隔离。由电压调节器提供的电压优选地通过用来自电压调节器的电压为DRAM中的每个n检测放大器供电而耦合到存取晶体管。

9. 发明授权

US06735103B2 System and method to avoid voltage read errors in open digit line array dynamic random access memories 有权
标题翻译：系统和方法，以避免开放数字线阵列动态随机存取存储器中的电压读取错误
公开(公告)号：US06735103B2
公开(公告)日：2004-05-11
申请号：US10231680
申请日：2002-08-29
申请人： Howard C. Kirsch
发明人： Howard C. Kirsch
IPC分类号： G11C502
CPC分类号： G11C11/4074 , G11C7/18 , G11C11/4097 , G11C2211/4068
摘要： Selective coupling devices directed by coupling controllers prevent cell plate and/or substrate disturbances from causing memory cell read and refresh errors in open digit line array memory devices. Using selective decoupling devices, when memory cells in an active row store an appreciably unbalanced number of either zeroes or ones, reading the cells generates a voltage transient in the cell plate and/or substrate that can be coupled to a reference digit line because the cell plates and/or substrates of the active sub-array are normally coupled to the cell plates and/or substrates of the reference arrays. By decoupling the cell plate and/or substrate of the active sub-array from the cell plates and/or substrates of the reference arrays, any coupling of the voltage transients to reference digit lines is reduced.
摘要翻译：由耦合控制器引导的选择耦合器件防止电池板和/或衬底干扰在开放数字线阵列存储器件中引起存储单元读取和刷新错误。使用选择性去耦装置，当活动行中的存储器单元存储零或非零数目的明显不平衡数量时，读取单元会在单元板和/或基板中产生可耦合到参考数字线的电压瞬变，因为单元有源子阵列的板和/或基板通常耦合到参考阵列的单元板和/或基板。通过将有源子阵列的单元板和/或衬底与参考阵列的单元板和/或衬底分离，减小了电压瞬变对参考数字线的任何耦合。

10. 发明授权

US5616941A Electrically programmable read-only memory cell 失效
标题翻译：电可编程只读存储单元
公开(公告)号：US5616941A
公开(公告)日：1997-04-01
申请号：US531357
申请日：1995-09-20
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： H01L21/8247 , H01L29/423 , H01C29/788 , H01C27/148
CPC分类号： H01L27/11521 , H01L29/42324
摘要： A floating gate (51)is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.
摘要翻译：浮动栅极（51）形成为具有增加浮动栅极（51）和存储单元的控制栅极之间的电容耦合的空腔（52）。存储单元可以用在EPROM，EEPROM和闪存EEPROM阵列中，并且可以通过热载流子注入，Fowler-Nordheim隧道等来编程和擦除。用于形成浮动栅极（51）的空腔（52）的工艺顺序具有良好的工艺裕度，允许一些光刻未对准。在一个实施例中，可以形成多层浮动栅极。多层结构允许电容耦合进一步增加而不占用更多的面积。

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