专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07194705B1 Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions 有权
标题翻译：在使用硬件描述语言电路描述的高级建模系统中对集成电路进行仿真
公开(公告)号：US07194705B1
公开(公告)日：2007-03-20
申请号：US10388692
申请日：2003-03-14
申请人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
发明人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.
摘要翻译：描述了使用电路的一个或多个电路描述语言表示来模拟建模系统内的集成电路的方法，装置和计算机可读介质。例如，电路的一个或多个电路描述语言表示的电路描述语言表示被转换成程序语言电路描述。执行第一模拟处理并从其获得输入数据。以输入数据作为参数输入来执行第二模拟处理以产生输出数据，第二模拟处理从程序语言电路描述导出。通过第二次模拟处理产生的输出数据被提供给第一个仿真过程。

2. 发明授权

US08868396B1 Verification and debugging using heterogeneous simulation models 有权
标题翻译：使用异构仿真模型进行验证和调试
公开(公告)号：US08868396B1
公开(公告)日：2014-10-21
申请号：US12605077
申请日：2009-10-23
申请人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
发明人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
摘要翻译：本文公开了一种用于验证和调试高级编程系统的电路设计模块的方法和装置。在高级编程环境中创建的电路设计必须经过多次转换，因为它被编译成可以在硬件中实现的形式。在每个变换步骤中，必须用仿真模型验证电路的行为，并且如果转换改变了电路的行为，则进行调试。所要求保护的发明提出了一种用于在不同仿真模型之间验证和调试的新方法，并通过利用高级电路设计的模块化结构来实现本领域的进步，以系统地识别不同仿真模型之间的模拟不匹配并确定电路的哪些部分设计负责的差异。

3. 发明授权

US07191412B1 Method and apparatus for processing a circuit description for logic simulation 有权
标题翻译：用于处理逻辑仿真的电路描述的方法和装置
公开(公告)号：US07191412B1
公开(公告)日：2007-03-13
申请号：US11238432
申请日：2005-09-28
申请人： Wei Lin , Sushama Ghanekar , Jimmy Zhenming Wang , Kumar Deepak
发明人： Wei Lin , Sushama Ghanekar , Jimmy Zhenming Wang , Kumar Deepak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Method and apparatus for processing a circuit description including a hierarchy of components for logic simulation is described. Each component is described using one of a first hardware description language (HDL) and a second HDL. A root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component is elaborated up to a cross-language boundary. The root component is described using one of the first HDL or the second HDL and each component at the cross-language boundary is described using the other of the first HDL or the second HDL. Each component at the cross-language boundary is stored in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language. A connection is established between each component at the cross-language boundary and a respective parent component.
摘要翻译：描述用于处理包括用于逻辑模拟的组件的层次的电路描述的方法和装置。使用第一硬件描述语言（HDL）和第二HDL之一描述每个组件。使用与根组件相同的HDL描述的根组件下的层次结构中的根组件和每个组件被阐述为跨语言边界。使用第一HDL或第二HDL中的一个描述根组件，并且使用第一HDL或第二HDL中的另一个来描述跨语言边界的每个组件。跨语言边界的每个组件基于语言存储在与第一HDL相关联的第一向量中的一个或与第二HDL相关联的第二向量中。在跨语言边界的每个组件和相应的父组件之间建立连接。

4. 发明授权

US08074077B1 Securing circuit designs within circuit design tools 有权
标题翻译：保护电路设计工具中的电路设计
公开(公告)号：US08074077B1
公开(公告)日：2011-12-06
申请号：US11786954
申请日：2007-04-12
申请人： Hem C. Neema , Kumar Deepak , Jimmy Zhenming Wang
发明人： Hem C. Neema , Kumar Deepak , Jimmy Zhenming Wang
IPC分类号： G06F12/14
CPC分类号： G06F21/6227
摘要： A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether the circuit design is protected. The method further can include permuting the plurality of elements of the string, encrypting the permuted string using a key shared with a circuit design tool, and including the permuted and encrypted string within the circuit design.
摘要翻译：确保电路设计的方法可以包括生成包括多个元件的串。多个元件可以包括从电路设计中选择的设计信息的元件和指示电路设计是否被保护的至少一个安全元件。该方法还可以包括对字符串的多个元素进行置换，使用与电路设计工具共享的密钥来加密置换的字符串，并且在电路设计中包括置换和加密的字符串。

5. 发明授权

US07721090B1 Event-driven simulation of IP using third party event-driven simulators 有权
标题翻译：使用第三方事件驱动模拟器进行事件驱动的IP仿真
公开(公告)号：US07721090B1
公开(公告)日：2010-05-18
申请号：US11370116
申请日：2006-03-07
申请人： Kumar Deepak , Satish R. Ganesan , Jimmy Zhenming Wang , Sundararajarao Mohan , Ralph D. Wittig , Hem C. Neema
发明人： Kumar Deepak , Satish R. Ganesan , Jimmy Zhenming Wang , Sundararajarao Mohan , Ralph D. Wittig , Hem C. Neema
IPC分类号： H04L29/06 , G06F21/00 , G06F12/14 , G06F17/50
CPC分类号： G06F21/12 , G06F17/5022 , G06F21/10 , G06F21/76 , G06F2217/66
摘要： A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.
摘要翻译：创建用于与基于软件的模拟器一起使用的电路设计的安全知识产权（IP）表示的方法可以包括将电路设计的硬件描述语言表示转换为加密的中间形式并编译电路设计的中间形式以产生加密的对象代码。该方法还可以包括将加密的对象代码与仿真内核库链接，从而创建电路设计的安全IP表示。安全IP可以包括电路设计的加密仿真模型和被配置为执行加密仿真模型的仿真内核。

6. 发明授权

US07197445B1 Atomic transaction processing for logic simulation 有权
标题翻译：用于逻辑仿真的原子事务处理
公开(公告)号：US07197445B1
公开(公告)日：2007-03-27
申请号：US10389126
申请日：2003-03-14
申请人： Kumar Deepak , Jimmy Zhenming Wang , Wei Lin
发明人： Kumar Deepak , Jimmy Zhenming Wang , Wei Lin
IPC分类号： G06F17/50 , G06F17/00 , G06F9/46 , G06F9/06 , G06F9/00
CPC分类号： G06F17/5022
摘要： A method (900) of modeling transactions and performing inertial rejection can include representing a plurality of scalar signals as one or more transaction objects, wherein each transaction object comprises a start index, an end index, values for each constituent scalar signal which correspond to an index within a range specified by the start index and end index inclusive, and a time at which the values are transacted. (400) The method further can include constructing and adding a new transaction object for the plurality of scalar signals (920) and comparing the new transaction object with at least one existing transaction object (925) wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window. At least one of a start index and an end index of the at least one existing transaction object can be manipulated (975).
摘要翻译：对交易进行建模和执行惯性拒绝的方法（900）可以包括将多个标量信号表示为一个或多个交易对象，其中每个交易对象包括开始索引，结束索引，每个组成标量信号的值对应于在由起始索引和结束索引（包括）指定的范围内的索引以及值被处理的时间。（400）该方法还可以包括为多个标量信号（920）构建和添加新的事务对象，并将新的事务对象与至少一个现有的事务对象（925）进行比较，其中至少一个现有的事务对象较早发生在新的交易对象的时间内，并且在拒绝窗口内。可以操纵至少一个现有交易对象的开始索引和结束索引中的至少一个（975）。

7. 发明授权

US08265918B1 Simulation and emulation of a circuit design 有权
标题翻译：电路设计的仿真和仿真
公开(公告)号：US08265918B1
公开(公告)日：2012-09-11
申请号：US12579846
申请日：2009-10-15
申请人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
发明人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5022
摘要： Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.
摘要翻译：协同仿真平台通常包括基于软件的系统和基于硬件的系统，其中电路设计的不同部分在基于软件的系统中模拟或在基于硬件的系统上仿真。在电路设计模型可以共同模拟之前，电路设计必须被转换和配置成可以与特定的基于硬件的系统执行和接口的形式。本发明的实施例提供了一种用于对电路设计的一部分进行协同仿真的方法，系统和制品，并且通过改进协同仿真配置和设置并提供协同仿真调整能力来实现本领域的进步运行。

8. 发明授权

US08768678B1 Scheduling processes in simulation of a circuit design based on simulation costs and runtime states of HDL processes 有权
标题翻译：基于HDL过程的仿真成本和运行时状态的电路设计仿真中的调度过程
公开(公告)号：US08768678B1
公开(公告)日：2014-07-01
申请号：US13245174
申请日：2011-09-26
申请人： Valeria Mihalache , Christopher H. Kingsley , Jimmy Z. Wang , Kumar Deepak
发明人： Valeria Mihalache , Christopher H. Kingsley , Jimmy Z. Wang , Kumar Deepak
IPC分类号： G06F9/45 , G06F9/455 , G06F17/00
CPC分类号： G06F9/4881 , G06F17/5009
摘要： One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.
摘要翻译：一个或多个实施例提供用于改善并行HDL模拟器的运行时性能的负载平衡解决方案。在编译期间，分析每个过程以基于HDL过程的复杂度来确定模拟成本。在仿真期间，使用在编译时计算的仿真成本来调度在相同模拟周期中执行的过程，以减少模拟期间产生的延迟。

9. 发明授权

US08838431B1 Mixed-language simulation 有权
标题翻译：混合语言模拟
公开(公告)号：US08838431B1
公开(公告)日：2014-09-16
申请号：US13027683
申请日：2011-02-15
申请人： Valeria Mihalache , Hem C. Neema , Kumar Deepak , Sonal Santan
发明人： Valeria Mihalache , Hem C. Neema , Kumar Deepak , Sonal Santan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.
摘要翻译：在一个实施例中，提供了一种用于产生用第一和第二HDL的组合描述的电路设计的数据流驱动的模拟代码的方法。详细描述电路描述，并生成电路描述的仿真数据流图。模拟代码，被配置为根据模拟数据流图以数据驱动方式对设计的执行进行建模，使用具有与第一HDL兼容的格式的第一HDL信号表示和具有与第一HDL信号表示相关联的第二HDL信号表示从数据流图生成，与第二HDL兼容的格式。对于模拟数据流图中跨越语言边界的电路描述的每个实例化模块，实例化模块的端口映射到第一HDL信号表示并映射到第二HDL信号表示。

10. 发明授权

US08495539B1 Scheduling processes in simulation of a circuit design 有权
标题翻译：电路设计仿真中的调度过程
公开(公告)号：US08495539B1
公开(公告)日：2013-07-23
申请号：US13347301
申请日：2012-01-10
申请人： Valeria Mihalache , Kumar Deepak , Hem C. Neema , Sonal Santan
发明人： Valeria Mihalache , Kumar Deepak , Hem C. Neema , Sonal Santan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.
摘要翻译：用于编译用于模拟的HDL规范的方法包括详细描述HDL规范并确定精心制作的电路设计的单驱动和多驱动网络。对于每个单独驱动的网络，分配相应的存储器位置以在运行时存储网络的相应驱动器的值。对于每个乘法驱动的网络，分配连续的内存块以在运行时存储网络的相应驱动程序的值。对于混合语言设计，此连续块包含所有涉及的所有HDL语言的驱动程序的值。生成模拟电路设计的仿真代码。对于每个单驱动网络，模拟代码被配置为将单驱动网络的相应驱动器的值存储在相应的存储器位置中。对于每个乘法驱动网络，模拟代码被配置为将相应驱动程序的值存储在指定的存储块中。生成的模拟代码被存储。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式