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1. 发明授权

US08495539B1 Scheduling processes in simulation of a circuit design 有权
标题翻译：电路设计仿真中的调度过程
公开(公告)号：US08495539B1
公开(公告)日：2013-07-23
申请号：US13347301
申请日：2012-01-10
申请人： Valeria Mihalache , Kumar Deepak , Hem C. Neema , Sonal Santan
发明人： Valeria Mihalache , Kumar Deepak , Hem C. Neema , Sonal Santan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.
摘要翻译：用于编译用于模拟的HDL规范的方法包括详细描述HDL规范并确定精心制作的电路设计的单驱动和多驱动网络。对于每个单独驱动的网络，分配相应的存储器位置以在运行时存储网络的相应驱动器的值。对于每个乘法驱动的网络，分配连续的内存块以在运行时存储网络的相应驱动程序的值。对于混合语言设计，此连续块包含所有涉及的所有HDL语言的驱动程序的值。生成模拟电路设计的仿真代码。对于每个单驱动网络，模拟代码被配置为将单驱动网络的相应驱动器的值存储在相应的存储器位置中。对于每个乘法驱动网络，模拟代码被配置为将相应驱动程序的值存储在指定的存储块中。生成的模拟代码被存储。

2. 发明授权

US08516413B1 Compilation and simulation of a circuit design 有权
标题翻译：电路设计的编译和仿真
公开(公告)号：US08516413B1
公开(公告)日：2013-08-20
申请号：US13468933
申请日：2012-05-10
申请人： Sandeep S. Deshpande , Hem C. Neema , Valeria Mihalache , Kumar Deepak , Sonal Santan , David K. Liddell
发明人： Sandeep S. Deshpande , Hem C. Neema , Valeria Mihalache , Kumar Deepak , Sonal Santan , David K. Liddell
IPC分类号： G06F9/45
CPC分类号： G06F17/5045 , G06F17/5022
摘要： One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.
摘要翻译：一个或多个实施例提供了一种HDL模拟方法，其确定编译期间整个电路设计的网络的依赖性，强制特性和强度特性。基于相应网的确定的特性，分别为每个网络生成模拟代码和数据结构。结果，不是为了实现能够处理每个可能的特征组合的每个网络的模拟实现代码，而是可以生成用于模拟网络的较不复杂的代码和数据结构。

3. 发明授权

US08838431B1 Mixed-language simulation 有权
标题翻译：混合语言模拟
公开(公告)号：US08838431B1
公开(公告)日：2014-09-16
申请号：US13027683
申请日：2011-02-15
申请人： Valeria Mihalache , Hem C. Neema , Kumar Deepak , Sonal Santan
发明人： Valeria Mihalache , Hem C. Neema , Kumar Deepak , Sonal Santan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.
摘要翻译：在一个实施例中，提供了一种用于产生用第一和第二HDL的组合描述的电路设计的数据流驱动的模拟代码的方法。详细描述电路描述，并生成电路描述的仿真数据流图。模拟代码，被配置为根据模拟数据流图以数据驱动方式对设计的执行进行建模，使用具有与第一HDL兼容的格式的第一HDL信号表示和具有与第一HDL信号表示相关联的第二HDL信号表示从数据流图生成，与第二HDL兼容的格式。对于模拟数据流图中跨越语言边界的电路描述的每个实例化模块，实例化模块的端口映射到第一HDL信号表示并映射到第二HDL信号表示。

4. 发明授权

US09135384B1 Compilation and simulation of a circuit design 有权
标题翻译：电路设计的编译和仿真
公开(公告)号：US09135384B1
公开(公告)日：2015-09-15
申请号：US13468942
申请日：2012-05-10
申请人： Sonal Santan , Hem C. Neema , Valeria Mihalache
发明人： Sonal Santan , Hem C. Neema , Valeria Mihalache
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/505
摘要： In one embodiment, a method for compiling an HDL specification for simulation of a circuit design is provided. Using one or more processors the circuit design is elaborated from the HDL specification. Two or more instances of a module of the elaborated design that have a same hardware configuration are determined. Simulation code that models the circuit design is generated. A first portion of the simulation code is configured to model the module having the hardware configuration. For each of the two or more instances, a second portion of the simulation code is configured to, in response to an indication to simulate the instance, execute the first portion of simulation code using a respective set of nets corresponding to the instance.
摘要翻译：在一个实施例中，提供了一种用于编译用于模拟电路设计的HDL规范的方法。使用一个或多个处理器，电路设计从HDL规范中阐述。确定具有相同硬件配置的精心设计的模块的两个或多个实例。生成模拟电路设计的仿真代码。仿真代码的第一部分被配置为对具有硬件配置的模块进行建模。对于两个或更多个实例中的每一个，模拟代码的第二部分被配置为响应于模拟该实例的指示，使用对应于该实例的相应的一组网来执行模拟代码的第一部分。

5. 发明授权

US08418095B1 Compilation and simulation of a circuit design 有权
标题翻译：电路设计的编译和仿真
公开(公告)号：US08418095B1
公开(公告)日：2013-04-09
申请号：US13468927
申请日：2012-05-10
申请人： Hem C. Neema , Sonal Santan , Kumar Deepak
发明人： Hem C. Neema , Sonal Santan , Kumar Deepak
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.
摘要翻译：一个或多个实施例提供了HDL模拟的方法，其确定网络的特性，例如在编译期间整个电路设计的网络的短路，非阻塞分配等。基于相应网的确定的特性，分别为每个网络生成模拟代码和数据结构。结果，不是为了实现能够处理每个可能的特征组合的每个网络的模拟实现代码，而是可以生成用于模拟网络的较不复杂的代码和数据结构。

6. 发明授权

US08327311B1 Generating a simulation model of a circuit design 有权
标题翻译：生成电路设计的仿真模型
公开(公告)号：US08327311B1
公开(公告)日：2012-12-04
申请号：US13188407
申请日：2011-07-21
申请人： Hem C. Neema , Sonal Santan , Kumar Deepak
发明人： Hem C. Neema , Sonal Santan , Kumar Deepak
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5022 , G06F2217/84
摘要： Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.
摘要翻译：在仿真模型中生成激活过程的功能的方法。确定电路设计网的多个位的至少两个相互排斥的子范围。确定与多个位的每个子范围相关联的相应处理集。唤醒功能的规范包括对于多个比特的每个子范围，对多个比特的子范围中的至少一个比特的值的变化的测试以及相关联的每个进程的启动响应于检测到的至少一个位的值的改变而设置的处理。该规范还包括响应于子范围中的一个子范围中检测到的至少一个比特的值的改变的控制，其绕过用于子范围中的至少另一个中的至少一个比特的值的改变的测试。

7. 发明授权

US09117043B1 Net sensitivity ranges for detection of simulation events 有权
标题翻译：用于检测模拟事件的净灵敏度范围
公开(公告)号：US09117043B1
公开(公告)日：2015-08-25
申请号：US13523799
申请日：2012-06-14
申请人： Lixin Huang , Hem C. Neema , Sonal Santan
发明人： Lixin Huang , Hem C. Neema , Sonal Santan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036 , G06F17/5045
摘要： Processing a circuit design can include determining a first set of net sensitivity ranges for a net of the circuit design, wherein at least two net sensitivity ranges of the first set are partially overlapping, and translating the first set of net sensitivity ranges into a second set of net sensitivity ranges comprising a plurality of member net sensitivity ranges with no partially overlapping member net sensitivity ranges. A net sensitivity tree can be constructed that includes hierarchically ordered nodes. Each node can specify a net sensitivity range of one member of the second set of net sensitivity ranges.
摘要翻译：处理电路设计可以包括确定电路设计网的第一组净灵敏度范围，其中第一组的至少两个净灵敏度范围部分重叠，并将第一组净灵敏度范围转换为第二组的净灵敏度范围包括多个成员净敏感范围，没有部分重叠的成员净敏感度范围。可以构造包括分层有序节点的净灵敏度树。每个节点可以指定第二组净灵敏度范围的一个成员的净灵敏度范围。

8. 发明授权

US07403961B1 Dangling reference detection and garbage collection during hardware simulation 有权
标题翻译：硬件仿真期间悬挂参考检测和垃圾收集
公开(公告)号：US07403961B1
公开(公告)日：2008-07-22
申请号：US10388935
申请日：2003-03-14
申请人： Kumar Deepak , Sushama Ghanekar , Sonal Santan
发明人： Kumar Deepak , Sushama Ghanekar , Sonal Santan
IPC分类号： G06F12/00 , G06F17/30 , G06F17/50 , G06F11/00
CPC分类号： G06F12/0253 , G06F17/5022 , Y10S707/99957
摘要： A method of dangling reference detection and garbage collection of VHDL objects within a program includes the steps of providing an Access Value having an Object Reference pointing to an Allocated Object and having and an Access Count pointer pointing to an integer object named Access Count which models a shared access count for the access values. The method sets the Object Reference and the Access Count pointer to null when constructing a new access value and enables an assignment of a negative Access Count to the shared access count when de-allocating a pointer to the Allocated Object. The method also maintains an exact count of a number of pointers pointing to the Allocated Object.
摘要翻译：一种在程序中悬挂参考检测和VHDL对象的垃圾收集的方法，包括以下步骤：提供具有指向分配对象的对象引用的访问值，并具有指向指向访问计数的整数对象的访问计数指针，该整数对象对访问值的共享访问计数。当构造新的访问值时，该方法将“对象引用”和“访问计数”指针设置为“null”，并在将指针分配给“分配对象”时指定共享访问计数。该方法还维护指向分配对象的指针数量的精确计数。

9. 发明授权

US08560295B1 Suspension of procedures in simulation of an HDL specification 有权
标题翻译：暂停HDL规范模拟中的程序
公开(公告)号：US08560295B1
公开(公告)日：2013-10-15
申请号：US13027705
申请日：2011-02-15
申请人： Sonal Santan , Pratima Gupta
发明人： Sonal Santan , Pratima Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a method to simulate an HDL specification is provided. For each call to a procedure, an intermediate process is dynamically created during simulation. The process containing the call to the procedure is replaced with the intermediate process in an active process list of processes scheduled for execution. The intermediate process is configured to call the procedure and, in response to completing execution of the procedure, cause the simulator to add the calling process to the front of the active process list and remove the intermediate process from the active process list.
摘要翻译：在一个实施例中，提供了一种模拟HDL规范的方法。对于每个调用过程，在仿真期间动态创建一个中间过程。包含对该过程的调用的进程将被替换为计划执行的进程的活动进程列表中的中间进程。中间过程被配置为调用过程，并且响应于完成该过程的执行，使得模拟器将调用进程添加到活动进程列表的前面，并从活动进程列表中移除中间进程。

10. 发明授权

US08751210B1 Suspending procedures in simulation of a circuit design 有权
标题翻译：电路设计仿真中暂停程序
公开(公告)号：US08751210B1
公开(公告)日：2014-06-10
申请号：US12619623
申请日：2009-11-16
申请人： Sonal Santan
发明人： Sonal Santan
IPC分类号： G06F17/50 , G06G7/62 , G06F9/455 , G06F9/45
CPC分类号： G06F17/5022
摘要： When a wait statement is encountered in an HDL simulation, the simulation kernel executes functions corresponding to other processes while waiting for the wait to mature. However, the preservation of variables and states of each process and procedure in the call chain can be complex and inefficient. An embodiment of the present invention provides a method to suspend procedures in simulation of an HDL circuit design such that processes that call procedures containing wait statements are executed on a secondary runtime stack and can be suspended by saving the state of simulation and switching simulation execution to the primary runtime stack.
摘要翻译：当在HDL仿真中遇到等待语句时，模拟内核在等待等待成熟时执行与其他进程相对应的功能。然而，调用链中每个进程和过程的变量和状态的保存可能是复杂和低效的。本发明的实施例提供了一种在HDL电路设计仿真中暂停程序的方法，使得在二次运行时栈上执行包含等待语句的过程的处理，并且可以通过将仿真状态和切换仿真执行保存到主运行时堆栈。

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