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1. 发明授权

US5723909A Semiconductor device and associated fabrication method 失效
标题翻译：半导体器件及相关制造方法
公开(公告)号：US5723909A
公开(公告)日：1998-03-03
申请号：US712237
申请日：1996-09-11
申请人： Kousaku Yano , Tatsuo Sugiyama , Satoshi Ueda , Noboru Nomura
发明人： Kousaku Yano , Tatsuo Sugiyama , Satoshi Ueda , Noboru Nomura
IPC分类号： H01L21/205 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L2924/0002
摘要： A first metallization layer is locally formed on the surface of a semiconductor substrate thereby leaving portions of the semiconductor substrate's surface exposed. A first silicon oxide layer is then formed in such a manner that it covers the exposed portions of the semiconductor substrate's surface and the first metallization layer. This is followed by the formation of an HMDS molecular layer on the first silicon oxide layer. Then, a second silicon oxide is formed on the molecular layer by means of a CVD process utilizing the chemical reaction of ozone with TEOS. Finally, a second metallization layer is locally formed on the second silicon oxide layer.
摘要翻译：第一金属化层局部地形成在半导体衬底的表面上，从而使半导体衬底表面的部分露出。然后以这样的方式形成第一氧化硅层，使得其覆盖半导体衬底的表面和第一金属化层的暴露部分。随后在第一氧化硅层上形成HMDS分子层。然后，通过使用臭氧与TEOS的化学反应的CVD工艺在分子层上形成第二氧化硅。最后，第二金属化层局部形成在第二氧化硅层上。

2. 发明授权

US5753536A Semiconductor device and associated fabrication method 失效
标题翻译：半导体器件及相关制造方法
公开(公告)号：US5753536A
公开(公告)日：1998-05-19
申请号：US520252
申请日：1995-08-28
申请人： Tatsuo Sugiyama , Shuji Hirao , Kousaku Yano , Noboru Nomura
发明人： Tatsuo Sugiyama , Shuji Hirao , Kousaku Yano , Noboru Nomura
IPC分类号： H01L21/98 , H01L25/065 , H01L21/60
CPC分类号： H01L23/544 , H01L21/76898 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2224/0401 , H01L2224/05571 , H01L2224/08145 , H01L2224/13099 , H01L2224/80141 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/81121 , H01L2224/81801 , H01L2224/81894 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3511
摘要： A first electrode and a first insulating layer of electrode insulation are formed on a first semiconductor substrate. A second electrode and a second insulating layer of electrode insulation are formed on a second semiconductor substrate. The first semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement. Likewise, the second semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement, wherein the pattern of the second semiconductor substrate has a phase shift of 180 degrees with respect to the pattern of the first semiconductor substrate. The first and second semiconductor substrates are bonded together with their patterns in engagement.
摘要翻译：在第一半导体衬底上形成有电极绝缘体的第一电极和第一绝缘层。在第二半导体衬底上形成第二电极和电极绝缘的第二绝缘层。第一半导体衬底在其表面上以条纹布置的规则间隔在其表面处具有凹槽/突起的图案（即横截面的锯齿形图案）。类似地，第二半导体衬底在其表面上在条纹布置中以规则的间隔在其表面处具有凹槽/突起的图案（即，横截面的锯齿形图案），其中第二半导体衬底的图案具有180度的相移，相对于第一半导体衬底的图案。第一和第二半导体衬底以它们的图案接合在一起。

3. 发明授权

US5576247A Thin layer forming method wherein hydrophobic molecular layers preventing a BPSG layer from absorbing moisture 失效
标题翻译：疏水分子层防止BPSG层吸收水分的薄层形成方法
公开(公告)号：US5576247A
公开(公告)日：1996-11-19
申请号：US97231
申请日：1993-07-27
申请人： Kousaku Yano , Masayuki Endo , Yuka Terai , Noboru Nomura , Tomoyasu Murakami , Tetsuya Ueda , Satoshi Ueda
发明人： Kousaku Yano , Masayuki Endo , Yuka Terai , Noboru Nomura , Tomoyasu Murakami , Tetsuya Ueda , Satoshi Ueda
IPC分类号： H01L21/3105 , H01L21/316
CPC分类号： H01L21/3105 , Y10S438/974
摘要： A BPSG layer serving as a silicon oxide layer is formed on a semiconductor substrate 1. Formed on the surface of the BPSG layer is a hydrophobic molecular layer comprising hydrophobic groups such as methyl, ethyl and the like, by a silylation reaction (in which silyl having hydrophobic groups such as methyl groups, ethyl groups and the like, is reacted with OH groups, and in which the hydrophobic groups are substituted with H of the OH groups to generate --O--Si(CH.sub.3).sub.3 or the like). The molecular layer prevents the BPSG layer from absorbing moisture.
摘要翻译：在半导体衬底1上形成用作氧化硅层的BPSG层。在BPSG层的表面上形成疏水性分子层，其通过甲硅烷基化反应（甲基，具有疏水基团如甲基，乙基等与OH基团反应，并且其中疏水基团被H的OH基团取代以产生-O-Si（CH 3）3等）。分子层防止BPSG层吸湿。

4. 发明授权

US5501739A Apparatus and method for forming thin film 失效
标题翻译：用于形成薄膜的装置和方法
公开(公告)号：US5501739A
公开(公告)日：1996-03-26
申请号：US158305
申请日：1993-11-29
申请人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
发明人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
IPC分类号： H01L21/205 , B05D1/18 , B05D7/24 , C23C16/54 , H01L21/302 , C23C16/00
CPC分类号： B82Y30/00 , B05D1/185 , B05D1/60 , B82Y40/00 , C23C16/54
摘要： A forming apparatus of a thin film includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate. A feeding device is provided in the processing chamber for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film includes the steps of forming the thin film on the surface of the supplied substrate in the processing chamber, and feeding material for forming the organic molecular layer, including silicon or germanium, on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.
摘要翻译：薄膜的形成装置包括处理室，其中在所提供的基板的表面上进行预定的处理。在处理室中设置有供给装置，用于供给材料以在基板的表面上形成包括硅或锗的有机分子层。薄膜的形成方法包括以下步骤：在处理室中供应的基板的表面上形成薄膜，以及在表面上形成的薄膜上形成有机分子层（包括硅或锗）的材料通过处理室中的进料装置，然后在基材表面上形成有机分子层。

5. 发明授权

US5863338A Apparatus and method for forming thin film 失效
标题翻译：用于形成薄膜的装置和方法
公开(公告)号：US5863338A
公开(公告)日：1999-01-26
申请号：US583662
申请日：1996-01-05
申请人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
发明人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
IPC分类号： H01L21/205 , B05D1/18 , B05D7/24 , C23C16/54 , H01L21/302 , C23C16/00
CPC分类号： B82Y30/00 , B05D1/185 , B05D1/60 , B82Y40/00 , C23C16/54
摘要： A forming apparatus of a thin film, includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate, and a feeding device, which is provided in the processing chamber, for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film, includes steps of forming a thin film on a surface of a supplied substrate in a processing chamber, and feeding material for forming an organic molecular layer including silicon or germanium on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.
摘要翻译：薄膜的成形装置包括处理室，其中在所提供的基板的表面上执行预定的处理;以及馈送装置，其设置在处理室中，用于馈送材料以形成有机分子层，所述有机分子层包括硅或锗在基板的表面上。薄膜的形成方法包括以下步骤：在处理室中的供给的基板的表面上形成薄膜，以及在所形成的薄膜上形成包含硅或锗的有机分子层的供给材料基板通过处理室中的进料装置，然后在基板的表面上形成有机分子层。

6. 发明授权

US5312776A Method of preventing the corrosion of metallic wirings 失效
标题翻译：防止金属布线腐蚀的方法
公开(公告)号：US5312776A
公开(公告)日：1994-05-17
申请号：US977022
申请日：1992-11-16
申请人： Tomoyasu Murakami , Michinari Yamanaka , Kousaku Yano , Masayuki Endo , Noboru Nomura , Staoshi Ueda , Naoto Matsuo , Hiroshi Imai , Masafumi Kubota
发明人： Tomoyasu Murakami , Michinari Yamanaka , Kousaku Yano , Masayuki Endo , Noboru Nomura , Staoshi Ueda , Naoto Matsuo , Hiroshi Imai , Masafumi Kubota
IPC分类号： H01L21/02 , H01L21/3213 , H01L23/532 , H01L71/44
CPC分类号： H01L21/02071 , H01L23/5329 , H01L2924/0002 , Y10S148/131
摘要： According to the method of preventing the corrosion of metallic wirings of the present invention, aluminium alloy wirings are formed on the surface of a substrate with the use of photoresists, and the photoresists are then removed. Thereafter, HMDS (hexamethyl disilazine) serving as a surface-active agent or its derivative is supplied to the aluminium alloy wirings to form hydrophobic molecular layers on the lateral walls of the aluminium alloy wirings.
摘要翻译：根据本发明的防止金属配线的腐蚀的方法，使用光致抗蚀剂在基板的表面上形成铝合金布线，然后除去光致抗蚀剂。此后，将作为表面活性剂或其衍生物的HMDS（六甲基二硅嗪）供给到铝合金布线，以在铝合金布线的侧壁上形成疏水性分子层。

7. 发明授权

US5385867A Method for forming a multi-layer metallic wiring structure 失效
标题翻译：用于形成多层金属布线结构的方法
公开(公告)号：US5385867A
公开(公告)日：1995-01-31
申请号：US216968
申请日：1994-03-24
申请人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
发明人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/283 , H01L21/31
CPC分类号： H01L21/76847 , H01L21/76844 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L2924/0002 , Y10S438/948
摘要： After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.
摘要翻译：在硅衬底上积累BPSG膜层之后，第一Al-Si-Cu膜层，W膜层和第二Al-Si-Cu膜层依次堆积在该BPSG膜层上。在第二Al-Si-Cu膜层上形成具有宽幅和窄宽图案部分的抗蚀剂图案。宽幅图形部分设置在与用于连接第一层金属布线和第二层金属布线的接触件相对应的位置处，而窄宽图案部分设置在与布线部分相对应的位置处第一层金属布线。在具有抗蚀剂图案的掩模的第二Al-Si-Cu膜层上施加第一蚀刻之后，在W膜层上施加第二蚀刻。此后，通过施加第三蚀刻，去除残留在第一层金属布线上的抗蚀剂图案，并将第一Al-Si-Cu膜层变形为高金属膜部分和短金属膜部分。在第一Al-Si-Cu膜层上积累层间绝缘膜层之后，在该层间绝缘膜层上施加回蚀，直到高金属膜部分的顶部露出。然后，在层间绝缘膜层上形成第二层金属布线，使得第二层金属布线与高金属膜部分连接。

8. 发明授权

US5569628A Semiconductor device fabrication method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US5569628A
公开(公告)日：1996-10-29
申请号：US535323
申请日：1995-09-27
申请人： Kousaku Yano , Tomoyasu Murakami , Masayuki Endo , Noboru Nomura
发明人： Kousaku Yano , Tomoyasu Murakami , Masayuki Endo , Noboru Nomura
IPC分类号： H01L21/28 , H01L21/768 , H01L21/465
CPC分类号： H01L21/76841 , H01L21/76843
摘要： A silicon dioxide film is partly etched away to form an opening thereby exposing a silicon substrate. The surface of the opening, which is almost entirely covered with Si-OH, is coated with hexamethyldisilazane (HMDS) to bring about a silylation reaction. This causes the silicon substrate surface to be covered with a molecular film formed by replacing the hydrogen part in Si-OH with Si((CH.sub.3).sub.3. Atoms of aluminum are ejected by a sputtering process. The ejected aluminum atoms collide with the molecular film. Although some hydrocarbons (CH.sub.x) are sputtered or ejected due to such collision, a SiO.sub.x C.sub.y H.sub.z film 12' transformed from the molecular film is left between an aluminum film deposited and the silicon substrate. This SiO.sub.x C.sub.y H.sub.z film 12' acts as a barrier metal. The presence of the SiO.sub.x C.sub.y H.sub.z film prevents the occurrence of counter diffusion in the Al-Si system. No spikes are formed as a result.
摘要翻译：部分地蚀刻掉二氧化硅膜以形成开口，从而暴露硅衬底。几乎完全用Si-OH覆盖的开口的表面涂覆有六甲基二硅氮烷（HMDS）以进行甲硅烷基化反应。这导致硅衬底表面被用Si（（CH 3）3代替Si-OH中的氢部分而形成的分子膜覆盖，铝的原子通过溅射工艺喷射，喷射的铝原子与分子膜碰撞虽然由于这种碰撞而使一些烃类（CHx）溅射或喷射，但是从分子膜转化的SiO x C y H z膜12'留在沉积的铝膜和硅基板之间，该SiOxCyHz膜12'作为阻挡金属， SiOxCyHz膜的存在防止了在Al-Si系统中产生反向扩散，结果不形成尖峰。

9. 发明授权

US5986313A Semiconductor device comprising MISFETS and method of manufacturing the same 失效
标题翻译：包括MISFET的半导体器件及其制造方法
公开(公告)号：US5986313A
公开(公告)日：1999-11-16
申请号：US988776
申请日：1997-12-11
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for ccntact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准来形成用于与有源区域成反射的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

10. 发明授权

US5733812A Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same 失效
标题翻译：具有具有较低电阻杂质扩散层的场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5733812A
公开(公告)日：1998-03-31
申请号：US571131
申请日：1995-12-12
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for contact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准形成来自用于与有源区接触的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

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