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1. 发明授权

US07013456B1 Profiling execution of computer programs 有权
标题翻译：分析计算机程序的执行情况
公开(公告)号：US07013456B1
公开(公告)日：2006-03-14
申请号：US09334530
申请日：1999-06-16
申请人： Korbin S. Van Dyke , Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Stephen C. Purcell , Niteen Aravind Patkar
发明人： Korbin S. Van Dyke , Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Stephen C. Purcell , Niteen Aravind Patkar
IPC分类号： G06F9/44
CPC分类号： G06F9/45533 , G06F9/45541 , G06F9/45554
摘要： A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.
摘要翻译：一种用于执行该方法的方法和计算机。在计算机上执行程序时，检测到在指令流水线中发生的可轮廓事件。该指令流水线用于记录描述可概要事件的简档信息，基本上与可概要事件的发生同时发生。检测和记录在没有软件干预的情况下在计算机硬件的控制下进行。

2. 发明授权

US06826748B1 Profiling program execution into registers of a computer 有权
标题翻译：将程序执行分析到计算机的寄存器中
公开(公告)号：US06826748B1
公开(公告)日：2004-11-30
申请号：US09339749
申请日：1999-06-24
申请人： Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
发明人： Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
IPC分类号： G06F944
CPC分类号： G06F9/45558 , G06F9/45541 , G06F9/45554 , G06F2009/45583
摘要： A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.
摘要翻译：用于执行该方法的方法和计算机。在计算机上执行程序时，计算机使用通用寄存器文件的寄存器来存储指令结果。描述可概要事件的简档信息可记录在通用寄存器文件中，因为可以描述事件的发生，而无需先将信息捕获到计算机的主存储器中。

3. 发明授权

US06941545B1 Profiling of computer programs executing in virtual memory systems 有权
标题翻译：在虚拟内存系统中执行的计算机程序的分析
公开(公告)号：US06941545B1
公开(公告)日：2005-09-06
申请号：US09322443
申请日：1999-05-28
申请人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
发明人： David L. Reese , John S. Yates, Jr. , Paul H. Hohensee , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
IPC分类号： G06F9/455 , G06F9/44
CPC分类号： G06F9/45554 , G06F9/45541 , G06F9/45558 , G06F2009/45583
摘要： A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.
摘要翻译：一台电脑。指令流水线和存储器访问单元在计算机的存储器的逻辑地址空间中执行指令。地址转换电路将由程序生成的地址参考从程序的逻辑地址空间转换为计算机的物理地址空间。简档电路与指令流水线协作地互连，并且被配置为在没有编译器帮助执行分析的情况下检测在指令流水线中发生的可概要事件的发生，并且与存储器访问单元协作地互连以记录描述参考的物理存储器地址的简档信息程序的执行间隔。

4. 发明授权

US08065504B2 Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor 有权
标题翻译：使用由指令地址索引的片上和片外查找表来控制处理器中的指令执行
公开(公告)号：US08065504B2
公开(公告)日：2011-11-22
申请号：US11004729
申请日：2004-12-02
申请人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
发明人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
IPC分类号： G06F9/30
CPC分类号： G06F9/45533
摘要： A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.
摘要翻译：微处理器芯片具有指令流水线电路和指令分类电路，它们将执行的指令分类为少量类并记录分类代码值。片上表具有对应于存储器的一系列地址的条目，并且被设计为保持在计算机的存储器中查看片外表的值的统计评估。查找电路被设计为从微处理器的基本指令处理周期的一部分获取片上表格中的条目。掩码至少部分由定时器设置的值。基于与所处理的指令的地址，掩码的当前值，记录的分类代码和片外表相对应的片上表项的值来控制指令流水线电路。

5. 发明授权

US07228404B1 Managing instruction side-effects 有权
标题翻译：管理指令副作用
公开(公告)号：US07228404B1
公开(公告)日：2007-06-05
申请号：US09672440
申请日：2000-09-28
申请人： Ronak Patel , Korbin S. Van Dyke , T.R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Sanjay Mansingh , Paul William Campbell
发明人： Ronak Patel , Korbin S. Van Dyke , T.R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Sanjay Mansingh , Paul William Campbell
IPC分类号： G06F9/00
CPC分类号： G06F9/30174 , G06F9/3851 , G06F9/3861
摘要： A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. Instruction execution is monitored for a condition that is a superset of a condition whose occurrence is desired to be detected, and a first exception is raised as a result of recognizing the superset condition. Software filters the superset condition to determine whether the monitored condition has occurred, and if so, the software establishes a second exception to be raised after execution of further instructions of the instruction stream. When it is recognized that an instruction is to affect the execution of a second instruction, the processor is set into single-step mode. After the second instruction is executed, the computer is set out of single-step mode.
摘要翻译：一台电脑。当识别到在建筑上可见的存储位置中要求建筑上可见的副作用的指令时，存储代表该副作用的结构可视表示的值，代表值的格式不同于体系结构副作用的隐形表示。恢复执行，而不产生架构上可见的副作用。之后，对应于代表值的架构可视化表示被写入架构可见的存储位置。在上下文切换中，写入第一进程的上下文并加载第二进程的上下文以使第二进程执行。至少一些指令在上下文资源集合之外保持存储资源的结果，并且标记指令以指示是否可以在标记指令的边界执行上下文切换。监视指示执行是作为期望发生的条件的超集的条件，并且作为识别超集条件的结果而引起第一异常。软件过滤超集条件以确定监视条件是否已经发生，如果是，则软件在执行指令流的进一步指令之后建立第二个异常。当识别到指令影响第二指令的执行时，处理器被设置为单步模式。执行第二条指令后，计算机将处于单步模式。

6. 发明授权

US06449671B1 Method and apparatus for busing data elements 失效
标题翻译：调用数据元素的方法和装置
公开(公告)号：US06449671B1
公开(公告)日：2002-09-10
申请号：US09328971
申请日：1999-06-09
申请人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
发明人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
IPC分类号： G06F1300
CPC分类号： G06F12/0806
摘要： A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.
摘要翻译：用于在计算系统内传送数据元素的方法和装置包括开始于在共享总线上提供在第一总线周期期间与第一事务相关的第一控制信号的处理。通过在第二总线周期期间提供与第二事务相关的第二控制信号和与第一事务相关的第一地址信号来继续处理。通过在第三总线周期期间提供与第三事务相关的第三控制信号和与第二事务相关的第二地址信号来继续处理。然后通过在第四总线周期期间提供与第一事务相关的第一状态和与第三事务相关的第三寻址信号来继续处理。然后通过在第五总线周期期间提供与第二事务相关的第二状态来继续处理。然后，当第一状态是命中时，通过提供与第一事务有关的第一数据继续处理，并在第六总线周期期间提供与第三事务有关的第三状态。

7. 发明授权

US06934832B1 Exception mechanism for a computer 有权
公开(公告)号：US06934832B1
公开(公告)日：2005-08-23
申请号：US09667226
申请日：2000-09-21
申请人： Korbin S. Van Dyke , Paul Campbell , Shalesh Thusoo , T. R. Ramesh , Alan McNaughton
发明人： Korbin S. Van Dyke , Paul Campbell , Shalesh Thusoo , T. R. Ramesh , Alan McNaughton
IPC分类号： G06F11/00
CPC分类号： G06F9/30174 , G06F9/3851 , G06F9/3861
摘要： A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers. The processor registers of the computer are designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory, the processor registers and general purpose registers of the computer together providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory.

8. 发明授权

US06643726B1 Method of manufacture and apparatus of an integrated computing system 有权
标题翻译：集成计算系统的制造方法和装置
公开(公告)号：US06643726B1
公开(公告)日：2003-11-04
申请号：US09376820
申请日：1999-08-18
申请人： Niteen Patkar , Ali Alasti , Don Van Dyke , Korbin Van Dyke , Shalesh Thusoo , Stephen C. Purcell , Govind Malalur
发明人： Niteen Patkar , Ali Alasti , Don Van Dyke , Korbin Van Dyke , Shalesh Thusoo , Stephen C. Purcell , Govind Malalur
IPC分类号： G06F1336
CPC分类号： G06F13/368
摘要： An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.
摘要翻译：集成计算系统包括形成在衬底上的至少一个处理器，其中处理器以处理器速率工作。集成计算系统还包括耦合到至少一个处理器并形成在基板上的全局总线。全局总线以等于或大于处理速率的速率支持事务（例如，数据，操作指令和/或控制信令传送）。集成计算系统还包括可操作地耦合到全局总线并形成在基板上的设备网关和存储器网关。设备网关为全局总线的至少一个设备（例如，内部或外部）提供接口。存储器网关提供全局总线和存储器之间的接口。

9. 发明授权

US06430646B1 Method and apparatus for interfacing a processor with a bus 有权
标题翻译：处理器与总线接口的方法和装置
公开(公告)号：US06430646B1
公开(公告)日：2002-08-06
申请号：US09377004
申请日：1999-08-18
申请人： Shalesh Thusoo , Niteen Patkar , Korbin Van Dyke , Stephen C. Purcell
发明人： Shalesh Thusoo , Niteen Patkar , Korbin Van Dyke , Stephen C. Purcell
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A method and apparatus for interfacing a processor with a bus includes processing that begins by storing transactions initiated by the processor into a buffer. The processing then continues by selecting one of the transactions stored in the buffer and placing the selected transaction on the bus. The processing continues by monitoring progress of fulfillment of each transaction in the buffer and flagging a transaction when it has been successfully completed. The processing also includes processing at least two related transactions prior to selecting one of the transactions from the buffer where, if transactions can be processed locally, they do not need to be transported on the bus. In addition, the processing includes monitoring the bus for related transactions initiated by another processor such that these transactions can be more efficiently processed. The related transaction on the bus would correspond to a transaction queued in the buffer.
摘要翻译：一种用于将处理器与总线接口的方法和装置包括通过将由处理器发起的事务存储到缓冲器中而开始的处理。然后，通过选择存储在缓冲器中的一个事务并将所选择的事务放置在总线上来继续处理。通过监视缓冲区中每个事务的执行进度并在事务成功完成时标记事务，继续进行处理。处理还包括在从缓冲器中选择一个事务之前处理至少两个相关事务，其中如果可以在本地处理事务，则它们不需要在总线上传输。此外，该处理包括监视由另一处理器发起的相关事务的总线，使得可以更有效地处理这些事务。总线上的相关事务将对应于在缓冲器中排队的事务。

10. 发明授权

US07240255B2 Area efficient BIST system for memories 有权
标题翻译：区域高效BIST系统用于记忆
公开(公告)号：US07240255B2
公开(公告)日：2007-07-03
申请号：US11088636
申请日：2005-03-22
申请人： Charles Akum Njinda , Shalesh Thusoo , Hao Wang
发明人： Charles Akum Njinda , Shalesh Thusoo , Hao Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/26 , G11C29/56012 , G11C2029/0401 , G11C2029/4402 , G11C2029/5602
摘要： A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with the particular DAL.
摘要翻译：具有用于IC的单个BIST的系统，其包括可能具有不同延迟，宽度和深度的多个存储器阵列。串行总线（可能是调试总线）连接BIST控制器，IC上的每个存储器阵列和控制器。每个存储器阵列具有关联的测试辅助逻辑（DAL）模块。与任何特定存储器阵列相关联的DAL识别来自用于相关联存储器阵列的BIST的命令，控制相关阵列的写入/读取命令的执行，并且在存储器阵列中读取的数据与适当的命令一起发送到比较器适用于相关阵列的延迟因此，有BIST的标准化命令，但是每个DAL以适合与特定DAL相关联的存储器阵列（或阵列）的方式执行这些命令。

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