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1. 发明授权

US07240255B2 Area efficient BIST system for memories 有权
标题翻译：区域高效BIST系统用于记忆
公开(公告)号：US07240255B2
公开(公告)日：2007-07-03
申请号：US11088636
申请日：2005-03-22
申请人： Charles Akum Njinda , Shalesh Thusoo , Hao Wang
发明人： Charles Akum Njinda , Shalesh Thusoo , Hao Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/26 , G11C29/56012 , G11C2029/0401 , G11C2029/4402 , G11C2029/5602
摘要： A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with the particular DAL.
摘要翻译：具有用于IC的单个BIST的系统，其包括可能具有不同延迟，宽度和深度的多个存储器阵列。串行总线（可能是调试总线）连接BIST控制器，IC上的每个存储器阵列和控制器。每个存储器阵列具有关联的测试辅助逻辑（DAL）模块。与任何特定存储器阵列相关联的DAL识别来自用于相关联存储器阵列的BIST的命令，控制相关阵列的写入/读取命令的执行，并且在存储器阵列中读取的数据与适当的命令一起发送到比较器适用于相关阵列的延迟因此，有BIST的标准化命令，但是每个DAL以适合与特定DAL相关联的存储器阵列（或阵列）的方式执行这些命令。

2. 发明授权

US6080203A Apparatus and method for designing a test and modeling system for a network switch device 失效
标题翻译：用于设计网络交换机设备的测试和建模系统的装置和方法
公开(公告)号：US6080203A
公开(公告)日：2000-06-27
申请号：US992798
申请日：1997-12-18
申请人： Charles Akum Njinda , Somnath Viswanath
发明人： Charles Akum Njinda , Somnath Viswanath
IPC分类号： G01R31/3185 , G06F17/50
CPC分类号： G01R31/318591
摘要： An arrangement for designing a testing modeling system provides a testing hierarchy, where non-standard device elements having internal memory and logic structures are modeled by partitioning the device element into a recognizable memory model and a recognizable logic model separate from the memory model. The segregated models are then verified for accuracy using existing design and simulation tool and with comparison to existing hardware implementations. Once the revised models have been verified, the new models can be stored in a model library for future use.
摘要翻译：用于设计测试建模系统的布置提供了测试层级，其中具有内部存储器和逻辑结构的非标准设备元件通过将设备元件划分成可识别存储器模型和与存储器模型分离的可识别逻辑模型来建模。然后使用现有的设计和仿真工具，并与现有的硬件实现进行比较，验证隔离模型的准确性。一旦修正的模型已经被验证，新的模型可以存储在模型库中以供将来使用。

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