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1. 发明授权

US5852728A Uninterruptible clock supply apparatus for fault tolerant computer system 失效
标题翻译：用于容错计算机系统的不间断时钟提供装置
公开(公告)号：US5852728A
公开(公告)日：1998-12-22
申请号：US585344
申请日：1996-01-11
申请人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
发明人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
IPC分类号： G06F1/04 , G06F11/16 , G06F11/18 , G06F11/20 , G06F1/06
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1679 , G06F11/20
摘要： The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.
摘要翻译：本发明涉及双时钟源中的任何一个时钟源的时钟源切换，而不会影响双系统中的时钟输出，从而防止其中的处理器的故障。在本发明的容错计算机系统中，多个处理单元中的每一个包括时钟源，时钟选择器，时钟停止检测单元，时钟相位调整单元和相位一致检测/操作抑制/复位单元，由此在时钟故障的情况下，当从故障时钟源切换到正常时钟源时，时钟相位调整单元确保输出时钟信号的连续性。设置在时钟选择器的后续级中的时钟相位调整单元插入具有通过降低其环路滤波器的增益而获得的过阻抗响应特性的PLL电路。

2. 发明授权

US5841963A Dual information processing system having a plurality of data transfer channels 失效
标题翻译：双信息处理系统具有多个数据传输通道
公开(公告)号：US5841963A
公开(公告)日：1998-11-24
申请号：US861471
申请日：1997-05-21
申请人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
发明人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
IPC分类号： G06F11/16 , G06F15/17
CPC分类号： G06F11/1658
摘要： A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.
摘要翻译：由由多个数据传送单元连接的两个计算机系统和用于存储器副本的多个数据传送通道组成的双计算机系统，使得在从故障恢复时再次同步计算机系统。当数据传输通道没有发生故障时，数据传输单元在存储器复制操作中共享数据传输的负载，并且当在存储器复制操作期间在任何数据传送单元发生故障时，使用剩余的正常数据传送单元再次传送数据，从而高速地进行存储器复制，以便在从故障恢复时再次同步计算机系统，并且提高从故障恢复时的系统可靠性。

3. 发明授权

US6138248A Common disk unit multi-computer system 失效
标题翻译：普通磁盘机多计算机系统
公开(公告)号：US6138248A
公开(公告)日：2000-10-24
申请号：US1224
申请日：1997-12-30
申请人： Masahiko Saito , Hidehito Takewa , Kenichi Kurosawa , Yoshihiro Miyazaki , Shigenori Kaneko
发明人： Masahiko Saito , Hidehito Takewa , Kenichi Kurosawa , Yoshihiro Miyazaki , Shigenori Kaneko
IPC分类号： G06F11/20 , G06F11/16 , G06F12/08 , G06F15/16 , G06F15/177
CPC分类号： G06F11/20 , G06F11/0727 , G06F11/2028 , G06F11/2046 , G06F11/0793 , G06F11/2038
摘要： A computer and a backup computer exchange periodic report signal transmissions by way of SVP115. When there is no periodic report signal transmission from the main computer, the backup computer makes a main computer status inquiry and if one location is malfunctioning resets the main computer by way of the SVP115 and continues the processing. When permanent damage is present, the SVP115 continually resets the main computer and controls MOS switches of the common disk unit to isolate the SCSI from the main computer and continue the main computer processing.
摘要翻译：计算机和备份计算机通过SVP115交换周期性报告信号传输。当主计算机没有定期报告信号传输时，备份计算机进行主计算机状态查询，如果一个位置发生故障，则通过SVP115复位主机，并继续处理。当存在永久性损坏时，SVP115会连续复位主计算机，并控制公共磁盘单元的MOS开关，使SCSI与主计算机隔离，并继续进行主机处理。

4. 发明申请

US20060015231A1 Vehicle control system 有权
公开(公告)号：US20060015231A1
公开(公告)日：2006-01-19
申请号：US11094660
申请日：2005-03-31
申请人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
发明人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
IPC分类号： G06F19/00
CPC分类号： B60W30/00 , B60K6/46 , B60K6/52 , B60L3/0023 , B60L3/003 , B60L3/0076 , B60L3/0092 , B60L15/2009 , B60L2240/12 , B60L2240/20 , B60L2240/24 , B60L2240/423 , B60L2250/26 , B60T7/12 , B60W10/04 , B60W10/06 , B60W10/08 , B60W10/10 , B60W10/18 , B60W10/20 , B60W20/00 , B60W40/08 , B60W40/10 , B60W50/02 , B60W50/0225 , B60W50/04 , B60W2510/20 , B60W2510/202 , B60W2520/14 , B60W2540/10 , B60W2540/12 , B60W2550/20 , B62D5/046 , B62D5/0481 , B62D6/00 , G06F11/0796 , Y02T10/6217 , Y02T10/6265 , Y02T10/6286 , Y02T10/645 , Y02T10/72 , Y02T10/7275 , Y02T90/16
摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.

5. 发明授权

US06393509B2 Input/output device for connection and disconnection of active lines 有权
标题翻译：用于连接和断开有源线路的输入/输出设备
公开(公告)号：US06393509B2
公开(公告)日：2002-05-21
申请号：US09932973
申请日：2001-08-21
申请人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
发明人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
IPC分类号： G06F1300
CPC分类号： G06F13/4081 , G06F1/189 , Y02D10/14 , Y02D10/151
摘要： There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.
摘要翻译：提供了一种输入/输出装置，其在插入或移除时对连接到系统总线的其它扩展装置没有任何不利影响。扩展装置800包括电子电路400和MOS开关300，并且被连接通过具有长和短引脚的连接器连接到系统总线（BUS）。膨胀装置800是两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力和高阻抗保持电路通过一对长引脚稳定供电，为了可靠地将MOS开关300置于高阻抗状态，高阻抗保持电路350在扩展装置的内部驱动开/关控制端子，并且向来自不稳定电源260的电子电路400.在插入或移除时，不会对系统总线上的信号传输产生不利影响，并且降低对主电源的负载变化的影响。

6. 发明授权

US5287465A Parallel processing apparatus and method capable of switching parallel and successive processing modes 失效
标题翻译：并行处理装置和方法能够切换并行和连续的处理模式
公开(公告)号：US5287465A
公开(公告)日：1994-02-15
申请号：US549916
申请日：1990-07-09
申请人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
发明人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08 , G06F15/177 , G06F9/00
CPC分类号： G06F9/30189 , G06F9/30181 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.
摘要翻译：当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。指令根据处理状态判别标志在算术单元中进行处理。以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。此外，大量软件的兼容性的并行处理装置在不使用处理状态标志的情况下读出m个指令，对m个指令进行解码，检查第k个指令中是否存在转移指令，然后执行第一到第k + 1个算术单元中的第（k + 1）个指令，并且防止执行第（k + 2）至第m指令。通过执行第k个分支指令，并行处理装置计算其分支目的地的地址nm + h，执行计算以检查条件是否满足，然后防止执行地址nm到nm + h-1的指令并且执行地址nm + h至（n + 1）m的指令。以这种方式，并行处理装置执行多个指令，并连续执行分支指令。

7. 发明授权

US08645022B2 Vehicle control system 有权
标题翻译：车辆控制系统
公开(公告)号：US08645022B2
公开(公告)日：2014-02-04
申请号：US12575212
申请日：2009-10-07
申请人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
发明人： Kentaro Yoshimura , Kohei Sakurai , Nobuyasu Kanekawa , Yuichiro Morita , Yoshiaki Takahashi , Kenichi Kurosawa , Toshimichi Minowa , Masatoshi Hoshino , Yasuhiro Nakatsuka , Kotaro Shimamura , Kunihiko Tsunedomi , Shoji Sasaki
IPC分类号： G06F19/00 , G07C5/00
CPC分类号： B60W30/00 , B60K6/46 , B60K6/52 , B60L3/0023 , B60L3/003 , B60L3/0076 , B60L3/0092 , B60L15/2009 , B60L2240/12 , B60L2240/20 , B60L2240/24 , B60L2240/423 , B60L2250/26 , B60T7/12 , B60W10/04 , B60W10/06 , B60W10/08 , B60W10/10 , B60W10/18 , B60W10/20 , B60W20/00 , B60W40/08 , B60W40/10 , B60W50/02 , B60W50/0225 , B60W50/04 , B60W2510/20 , B60W2510/202 , B60W2520/14 , B60W2540/10 , B60W2540/12 , B60W2550/20 , B62D5/046 , B62D5/0481 , B62D6/00 , G06F11/0796 , Y02T10/6217 , Y02T10/6265 , Y02T10/6286 , Y02T10/645 , Y02T10/72 , Y02T10/7275 , Y02T90/16
摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.
摘要翻译：一种车辆控制系统，可以通过简化的ECU配置和低成本确保高可靠性，实时处理和可扩展性，通过整个系统中的协调备份错误，而不会增加单个控制器的冗余程度，超出最不必要的范围水平。车辆控制系统包括：传感器控制器，用于接收指示车辆的状态变量的传感器信号和从驾驶员施加的操作量;命令控制器，用于基于由传感器控制器接收的传感器信号产生控制目标值; 以及致动器控制器，用于从命令控制器接收控制目标值并操作致动器来控制车辆，这三个控制器经由网络互连。执行器控制器包括控制目标值产生单元，用于当由指令控制器产生的控制目标值异常时，基于由传感器控制器接收并由致动器控制器经由网络接收的传感器信号产生控制目标值;以及根据由控制目标值产生单元产生的控制目标值来控制致动器。

8. 发明申请

US20100211258A1 Vehicle Control System 有权
标题翻译：车辆控制系统
公开(公告)号：US20100211258A1
公开(公告)日：2010-08-19
申请号：US12772594
申请日：2010-05-03
申请人： Kohei SAKURAI , Yuichiro Morita , Masatoshi Hoshino , Yoshiaki Takahashi , Kenichi Kurosawa , Masahiro Matsubara
发明人： Kohei SAKURAI , Yuichiro Morita , Masatoshi Hoshino , Yoshiaki Takahashi , Kenichi Kurosawa , Masahiro Matsubara
IPC分类号： B60W50/02
CPC分类号： B60W50/0205
摘要： In a vehicle control system in which a large number of ECUs operate in coordination via a network, each node has an intra-network node status determination section, other node's status decision transmitting/other nodes' status decision receiving section, and failed-node identification section. The nodes exchange decisions made by the intra-network node status evaluation section with other nodes and thereby identify failed node.
摘要翻译：在大量ECU通过网络协调运行的车辆控制系统中，每个节点具有网络内节点状态确定部分，其他节点的状态判定发送/其他节点的状态判定接收部分和故障节点识别部分。节点将网络内节点状态评估部分作出的决定与其他节点进行交换，从而识别故障节点。

9. 发明授权

US07558483B2 Optical communication method, optical linking device and optical communication system 失效
标题翻译：光通信方法，光连接装置和光通信系统
公开(公告)号：US07558483B2
公开(公告)日：2009-07-07
申请号：US10897074
申请日：2004-07-23
申请人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
发明人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
IPC分类号： H04B10/00
CPC分类号： H04B10/271 , G06F13/4022 , H04B10/27 , H04B10/278
摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.
摘要翻译：该系统包括用于在所述电气总线未被驱动（OFF模式）下观察所述电动总线的模式和所述光纤的模式的光学总线桥接装置，使得通过光纤连接的两条电动总线的模式为使总线同时由多个节点驱动。虽然所述电气总线中的一个或两个已经被连接到其上的节点驱动（ON模式），但是已经从被驱动到所述光纤的总线连续地产生光输出，并且在从所述光纤输入光没有观察到所述总线的模式，而是向输入光的一侧的电力总线产生电力输出以驱动总线。光总线桥接装置在光总线桥接装置向光纤输出信号之后光纤在预定时间内不变化时，改变电气总线的模式。

10. 发明申请

US20070076593A1 Vehicle control system 有权
标题翻译：车辆控制系统
公开(公告)号：US20070076593A1
公开(公告)日：2007-04-05
申请号：US11528351
申请日：2006-09-28
申请人： Kohei Sakurai , Yuichiro Morita , Masatoshi Hoshino , Yoshiaki Takahashi , Kenichi Kurosawa , Masahiro Matsubara
发明人： Kohei Sakurai , Yuichiro Morita , Masatoshi Hoshino , Yoshiaki Takahashi , Kenichi Kurosawa , Masahiro Matsubara
IPC分类号： H04J3/14
CPC分类号： B60W50/0205
摘要： In a vehicle control system in which a large number of ECUs operate in coordination via a network, each node has an intra-network node status determination section, other node's status decision transmitting/other nodes status decision receiving section, and failed-node identification section. The nodes exchange decisions made by the intra-network node status evaluation section with other nodes and thereby identify failed node.
摘要翻译：在大量ECU通过网络协调运行的车辆控制系统中，每个节点具有网络内节点状态确定部分，其他节点的状态决定发送/其他节点状态判定接收部分和故障节点识别部分。节点将网络内节点状态评估部分作出的决定与其他节点进行交换，从而识别故障节点。

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