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1. 发明授权

US5968160A Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory 失效
标题翻译：根据程序的并行性通过使用高速缓冲存储器来处理多种模式的数据的方法和装置
公开(公告)号：US5968160A
公开(公告)日：1999-10-19
申请号：US923632
申请日：1997-09-04
申请人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
发明人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/08 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F9/3891 , G06F12/084 , G06F15/17381 , G06F15/8015 , G06F9/30087 , G06F9/3009 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3885
摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
摘要翻译：具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备同步。分别对应于多个处理器元件提供多个并行操作控制设备。数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。

2. 发明授权

US5287465A Parallel processing apparatus and method capable of switching parallel and successive processing modes 失效
标题翻译：并行处理装置和方法能够切换并行和连续的处理模式
公开(公告)号：US5287465A
公开(公告)日：1994-02-15
申请号：US549916
申请日：1990-07-09
申请人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
发明人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08 , G06F15/177 , G06F9/00
CPC分类号： G06F9/30189 , G06F9/30181 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.
摘要翻译：当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。指令根据处理状态判别标志在算术单元中进行处理。以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。此外，大量软件的兼容性的并行处理装置在不使用处理状态标志的情况下读出m个指令，对m个指令进行解码，检查第k个指令中是否存在转移指令，然后执行第一到第k + 1个算术单元中的第（k + 1）个指令，并且防止执行第（k + 2）至第m指令。通过执行第k个分支指令，并行处理装置计算其分支目的地的地址nm + h，执行计算以检查条件是否满足，然后防止执行地址nm到nm + h-1的指令并且执行地址nm + h至（n + 1）m的指令。以这种方式，并行处理装置执行多个指令，并连续执行分支指令。

3. 发明授权

US5784630A Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory 失效
公开(公告)号：US5784630A
公开(公告)日：1998-07-21
申请号：US367928
申请日：1995-01-03
申请人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
发明人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/08 , G06F15/173 , G06F15/80
CPC分类号： G06F9/3891 , G06F12/084 , G06F15/17381 , G06F15/8015 , G06F9/30087 , G06F9/3009 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3885
摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

4. 发明授权

US5561775A Parallel processing apparatus and method capable of processing plural instructions in parallel or successively 失效
标题翻译：能够并行或连续地处理多个指令的并行处理装置和方法
公开(公告)号：US5561775A
公开(公告)日：1996-10-01
申请号：US360081
申请日：1994-12-20
申请人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
发明人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08 , G06F15/177 , G06F9/445
CPC分类号： G06F9/30189 , G06F9/30181 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of integer logic arithmetic units for executing integer-arithmetic operations, a floating-point arithmetic unit for executing floating-point-arithmetic operations, and a control unit for controlling the plurality of integer-logic arithmetic units and the floating-point arithmetic unit to effect either parallel processing of a plurality of consecutive instructions stored in the instruction register in the plurality of integer-logic arithmetic units and the floating-point arithmetic unit, or successive processing of instructions stored in the instruction register in response to a processing state alteration instruction. The apparatus also includes a branch arithmetic unit for executing branch arithmetic operations. The branch arithmetic unit is controlled by the control unit to effect parallel or consecutive processing of instructions in conjunction with the integer-logic and floating-point arithmetic units.
摘要翻译：一种并行处理装置，包括用于指示要从存储器读出的指令的程序计数器，用于存储从由程序计数器指示的存储器的地址读出的多个连续指令的指令寄存器，多个整数逻辑运算用于执行整数运算的单元，用于执行浮点算术运算的浮点运算单元，以及用于控制多个整数运算单元的控制单元和浮点运算单元，以进行并行处理响应于处理状态改变指令，存储在多个整数逻辑运算单元和浮点运算单元中的指令寄存器中的多个连续指令或存储在指令寄存器中的指令的连续处理。该装置还包括用于执行分支算术运算的分支运算单元。分支运算单元由控制单元控制，以结合整数逻辑和浮点运算单元来执行指令的并行或连续处理。

5. 发明授权

US5404472A Parallel processing apparatus and method capable of switching parallel and successive processing modes 失效
标题翻译：并行处理装置和方法能够切换并行和连续的处理模式
公开(公告)号：US5404472A
公开(公告)日：1995-04-04
申请号：US149932
申请日：1993-11-10
申请人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
发明人： Kenichi Kurosawa , Shigeya Tanaka , Yasuhiro Nakatsuka , Tadaaki Bandoh
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08 , G06F15/177 , G06F9/445
CPC分类号： G06F9/30189 , G06F9/30181 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.
摘要翻译：当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。指令根据处理状态判别标志在算术单元中进行处理。以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。

6. 发明授权

US5506982A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
公开(公告)号：US5506982A
公开(公告)日：1996-04-09
申请号：US278245
申请日：1994-07-21
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/06
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

7. 发明授权

US06675311B2 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
标题翻译：数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US06675311B2
公开(公告)日：2004-01-06
申请号：US10002444
申请日：2001-12-06
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F104
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件。至少一对逻辑设备由时钟信号K1同步控制。

8. 发明授权

US07111187B2 Information processor and information processing system utilizing interface for synchronizing clock signal 失效
标题翻译：信息处理器和信息处理系统利用界面来同步时钟信号
公开(公告)号：US07111187B2
公开(公告)日：2006-09-19
申请号：US10701447
申请日：2003-11-06
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/04
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生与原始时钟信号K锁相并且具有预定占空比的至少一个第二时钟信号K 1 1和其操作时序被第二时钟信号K _{1 <1>，并且由至少一对逻辑器件之间提供的接口的操作时序由时钟信号K 1 1同步地控制。}

9. 发明授权

US5542083A Information processor and information processing system utilizing clock signal 失效
标题翻译：信息处理器和利用时钟信号的信息处理系统
公开(公告)号：US5542083A
公开(公告)日：1996-07-30
申请号：US460601
申请日：1995-06-02
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/04
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时至少一对逻辑器件由时钟信号K1同步控制。

10. 发明授权

US5974560A Information processor and information processing system utilizing clock signal 失效
标题翻译：信息处理器和利用时钟信号的信息处理系统
公开(公告)号：US5974560A
公开(公告)日：1999-10-26
申请号：US788831
申请日：1997-01-27
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/04
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时至少一对逻辑器件由时钟信号K1同步控制。

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