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1. 发明申请

US20060204858A1 Non-aqueous electrolyte secondary cell 审中-公开
标题翻译：非水电解质二次电池
公开(公告)号：US20060204858A1
公开(公告)日：2006-09-14
申请号：US11367276
申请日：2006-03-06
申请人： Koji Hasumi , Kentaro Takahashi , Takao Nishitani , Hiromitsu Suwa
发明人： Koji Hasumi , Kentaro Takahashi , Takao Nishitani , Hiromitsu Suwa
IPC分类号： H01M6/16
CPC分类号： H01M10/052 , H01M10/0567 , H01M10/0569 , H01M10/4235
摘要： It is an object of the present invention to provide a non-aqueous electrolyte secondary cell that is excellent in high-temperature preservation characteristics and in which an increase in the cell thickness is inhibited. The object is accomplished by the following structure. A non-aqueous electrolyte secondary cell having: a positive electrode; a negative electrode; a non-aqueous electrolyte having a non-aqueous solvent and an electrolytic salt; and an outer casing for housing the positive electrode, the negative electrode, and the non-aqueous electrolyte. The non-aqueous solvent has propylene carbonate at from 10 to 60 volume %. The non-aqueous electrolyte further has, as well as the non-aqueous solvent, vinyl acetate at from 0.3 to 3.0 mass % and vinyl ethylene carbonate at from 1.0 to 3.5 mass %.
摘要翻译：本发明的目的是提供高温保存特性优异且抑制细胞厚度增加的非水电解质二次电池。该目的通过以下结构来实现。一种非水电解质二次电池，具有：正极; 负极; 具有非水溶剂和电解质盐的非水电解质; 以及用于容纳正极，负极和非水电解质的外壳。非水溶剂具有10至60体积％的碳酸丙烯酯。非水电解质还含有0.3〜3.0质量％的乙酸乙烯酯和1.0〜3.5质量％的乙烯基碳酸亚乙酯，以及非水系溶剂。

2. 发明授权

US4796218A Arithmetic circuit capable of executing floating point operation and fixed point operation 失效
标题翻译：能够执行浮点运算和定点运算的算术电路
公开(公告)号：US4796218A
公开(公告)日：1989-01-03
申请号：US16036
申请日：1987-02-18
申请人： Hideo Tanaka , Takao Nishitani
发明人： Hideo Tanaka , Takao Nishitani
IPC分类号： G06F7/38 , G06F7/487 , G06F7/508 , G06F7/57
CPC分类号： G06F7/483 , G06F7/49936
摘要： An arithmetic circuit comprises a pair of input registers for holding a pair of given numbers, and a radix point adjustment circuit coupled to the input registers for aligning the radix points of the given numbers. This adjsutment circuit is capable of outputting at least a pair of radix point aligned fractions and one exponent derived from the radix point alignment. An arithmetic operation circuit receives the pair of the radix point aligned fractions, and outputs the result of a given arithmetic operation of the received fractions and generates an overflow signal when an overflow is generated in the arithmetic operation of the received fractions. An exponent correction circuit receives the exponent from the adjustment circuit, and is responsive to the overflow signal from the arithmetic operation circuit so as to selectively correct the received exponent. A fraction correction circuit receives the output of the arithmetic operation circuit so as to correct the received data. There is provided a first selector receiving the output of the exponent correction circuit and responsive to a given control signal so as to selectively output the output of the exponent correction circuit or a predetermined value. Further, a second selector is provided to receive the outputs of the arithmetic operation circuit and the fraction correction circuit so as to selectively output one of the two received fractions in response to the control signal.
摘要翻译：运算电路包括一对用于保持一对给定数字的输入寄存器，以及耦合到输入寄存器的基数点调整电路，用于对准给定数字的小数点。该调整电路能够输出至少一对小数点对齐分数和从小数点对齐导出的一个指数。算术运算电路接收一对基点对齐分数，并输出接收分数的给定算术运算结果，并在接收分数的算术运算中产生溢出时产生溢出信号。指数校正电路从调整电路接收指数，并响应于来自算术运算电路的溢出信号，以选择性地校正接收指数。分数校正电路接收算术运算电路的输出，以校正接收到的数据。提供了接收指数校正电路的输出并响应于给定控制信号的第一选择器，以选择性地输出指数校正电路的输出或预定值。此外，提供第二选择器以接收算术运算电路和分数校正电路的输出，以便响应于控制信号选择性地输出两个接收分数中的一个。

3. 发明授权

US4554670A System and method for ADPCM transmission of speech or like signals 失效
标题翻译：用于ADPCM传输语音或类似信号的系统和方法
公开(公告)号：US4554670A
公开(公告)日：1985-11-19
申请号：US484676
申请日：1983-04-13
申请人： Shinichi Aiko , Rikio Maruta , Takao Nishitani
发明人： Shinichi Aiko , Rikio Maruta , Takao Nishitani
IPC分类号： H03M3/04 , H04B1/66
CPC分类号： H03M3/042
摘要： An adaptive differential pulse code modulated (ADPCM) transmission system includes a subtractor for providing a difference signal E.sub.j between an input signal X.sub.j and a predicted signal X.sub.j. A coder encodes the difference signal E.sub.j into a coded signal U.sub.j for transmission to a receiver. The signal U.sub.j is also decoded at the transmitter to produce a reproduced error signal E.sub.j. A prediction circuit operates to generate a prediction signal X.sub.j on the basis of the reproduced error signal E.sub.j. The prediction circuit is controlled by a control circuit which operates to detect transmitter instability. A first level detector in the control circuit compares the input signal level against the level of a transmitter produced signal representing the input signal. A second level detector of the control circuit determines when the input signal is below a specified value. Transmitter instability is judged by a decision circuit which determines when the output of the first level detector exceeds a preset value and the output of the second level detector is below another preset value.
摘要翻译：自适应差分脉冲编码调制（ADPCM）传输系统包括用于在输入信号Xj和预测信号Xj之间提供差分信号Ej的减法器。编码器将差分信号Ej编码为编码信号Uj以传送到接收机。在发射机处也对信号Uj进行解码以产生再现的误差信号Ej。预测电路用于根据再现的误差信号Ej产生预测信号Xj。预测电路由操作以检测发射机不稳定性的控制电路控制。控制电路中的第一电平检测器将输入信号电平与表示输入信号的发射机产生信号的电平进行比较。控制电路的第二电平检测器确定输入信号何时低于规定值。发射机不稳定性由判定电路判定，判定电路确定第一电平检测器的输出何时超过预设值，第二电平检测器的输出低于另一预定值。

4. 发明授权

US4287558A Sampled data processing system having memory with areas alternately dedicated to data I/O and data processing 失效
标题翻译：具有交替专用于数据I / O和数据处理的区域的存储器的采样数据处理系统
公开(公告)号：US4287558A
公开(公告)日：1981-09-01
申请号：US944635
申请日：1978-09-21
申请人： Takao Nishitani
发明人： Takao Nishitani
IPC分类号： G06F3/00 , G01S7/28 , G06F13/12 , G06F13/16 , G06F13/28 , G06F15/00 , G06F3/05 , G06F13/00
CPC分类号： G06F13/1673 , G01S7/2806 , G06F13/282
摘要： A system for processing data received in the form of sample pulses has a memory with first and second major memory areas. A buffer register stores data temporarily to enable an interface between the timing of the system and of a sampled analog signal. A central processor processes data stored in one major memory area while data stored in the other major memory area is being transferred between the memory and the buffer register. The data transfer occurs during time periods while the central processor does not have access to the memory. One data item is outputted for each sample pulse received. This way, the cycle time of the sample pulses may be much greater than the cycle time of the central processor.
摘要翻译：用于处理以采样脉冲形式接收的数据的系统具有具有第一和第二主存储区的存储器。缓冲寄存器临时存储数据，以实现系统定时和采样模拟信号之间的接口。中央处理器处理存储在一个主存储区中的数据，而存储在另一个主存储区中的数据正在存储器和缓冲寄存器之间传送。数据传输发生在中央处理器无法访问存储器的时间段内。对于接收到的每个采样脉冲输出一个数据项。这样，采样脉冲的周期时间可能远大于中央处理器的周期时间。

5. 发明授权

US4899301A Signal processor for rapidly calculating a predetermined calculation a plurality of times to typically carrying out FFT or inverse FFT 失效
标题翻译：用于快速计算预定计算多次以通常执行FFT或逆FFT的信号处理器
公开(公告)号：US4899301A
公开(公告)日：1990-02-06
申请号：US8684
申请日：1987-01-29
申请人： Takao Nishitani , Yuichi Kawakami , Hideo Tanaka , Ichiro Kuroda
发明人： Takao Nishitani , Yuichi Kawakami , Hideo Tanaka , Ichiro Kuroda
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： In a signal processor for processing zeroth through (N-1)-th input signal elements into zeroth through (N-1)-th output signal elements, the input elements are initially stored, as memorized data, in respective memory addresses of a memory arrangement (11, 12) by a memory accessing arrangement which comprises a first address calculating arrangement (311, 321) for calculating a first address for the memory addresses. A distance indicating arrangement (312, 322) is for indicating an address distance from the first address among the memory addresses. By using the first address and the address distance a second address is calculated by a second address calculating arrangement (313, 323). A pair of stored data are read from the first and the second addresses as a pair of read data. A calculation performing circuit (20) is for performing a predetermined calculation on the pair of read data by using a coefficient read from a read-only memory (14) to produce a pair of calculated data which are stored in the first and the second addresses as the stored data. The calculation performing circuit performs the predetermined calculation a plurality of times to produce the output elements.
摘要翻译：在用于将第（N-1）个第（N-1）个输入信号元素处理为第零到第（N-1）个输出信号元件的信号处理器中，输入元件最初作为存储的数据存储在存储器的相应存储器地址中存储器访问装置（11,12）包括用于计算存储器地址的第一地址的第一地址计算装置（311,321）。距离指示装置（312,322）用于指示存储器地址中与第一地址的地址距离。通过使用第一地址和地址距离，第二地址由第二地址计算装置（313,323）计算。从第一和第二地址读取一对存储的数据作为一对读取数据。计算执行电路（20）用于通过使用从只读存储器（14）读取的系数来对该对读取数据执行预定计算，以产生存储在第一和第二地址中的一对计算数据作为存储的数据。计算执行电路多次执行预定的计算以产生输出元件。

6. 发明授权

US4817047A Processing circuit capable of raising throughput of accumulation 失效
标题翻译：处理电路能够提高积累的吞吐量
公开(公告)号：US4817047A
公开(公告)日：1989-03-28
申请号：US883703
申请日：1986-07-09
申请人： Takao Nishitani , Ichiro Kuroda , Hideo Tanaka , Kyosuke Sugishita
发明人： Takao Nishitani , Ichiro Kuroda , Hideo Tanaka , Kyosuke Sugishita
IPC分类号： E04H17/14 , G06F7/38 , G06F7/544 , G06F17/10 , H03H17/02 , G06F7/52
CPC分类号： G06F7/5443 , G06F17/10 , G06F7/49921
摘要： A digital signal processing circuit reduces the occurrence of overflow conditions during successive arithmetic operations. The product output of a multiplication circuit is shifted by a barrel shifter to round off a predetermined number of least significant bits, thereby reducing the occurrence of an overflow condition when the successive product outputs of the multiplication circuit are summed by an arithmetic logic unit (ALU) to produce a summed output. The summed output is then shifted toward the most significant bit by a predetermined number before an output signal is generated. An overflow detection and correction circuit is provided in the event of an overflow condition occurring either to the ALU or the barrel shifter.
摘要翻译：数字信号处理电路在连续的算术运算期间减少了溢出状况的发生。乘法电路的乘积输出由桶形移位器移位以舍弃预定数量的最低有效位，从而当乘法电路的连续乘积输出由算术逻辑单元（ALU）相加时减少溢出状况的发生）产生一个总和输出。然后，在产生输出信号之前，将相加的输出向最高有效位移位预定数。在ALU或桶形移位器发生溢出状况的情况下，提供溢出检测和校正电路。

7. 发明授权

US4700392A Speech signal detector having adaptive threshold values 失效
标题翻译：具有自适应阈值的语音信号检测器
公开(公告)号：US4700392A
公开(公告)日：1987-10-13
申请号：US643929
申请日：1984-08-24
申请人： Tadaharu Kato , Takao Nishitani
发明人： Tadaharu Kato , Takao Nishitani
IPC分类号： G10L11/02 , G10L5/00
CPC分类号： G10L25/78
摘要： Speech presence is detected by first comparing input signal absolute value versus a first threshold which is proportional to input signal RMS noise power, accumulating the first comparison output signal, then comparing the accumulated signal versus a second threshold signal which is proportional to a hangover time signal. The first and second threshold signals are used to form up to six threshold values.
摘要翻译：通过首先比较输入信号绝对值与与输入信号RMS噪声功率成比例的第一阈值来检测语音存在，累积第一比较输出信号，然后比较累积信号与延时时间信号成比例的第二阈值信号。第一和第二阈值信号用于形成多达六个阈值。

8. 发明授权

US4862173A Method and circuit for carrying out forward and inverse quantization by varying a reference step size 失效
标题翻译：通过改变参考步长进行正向和反向量化的方法和电路
公开(公告)号：US4862173A
公开(公告)日：1989-08-29
申请号：US858865
申请日：1986-05-01
申请人： Takao Nishitani
发明人： Takao Nishitani
IPC分类号： H04B14/04
CPC分类号： H04B14/046
摘要： A succession of input signals supplied to a quantizer is processed at sampling instants into a succession of quantized codes by step sizes with a current one of the quantized codes produced at each sampling instant with reference to a current step size adaptively decided not only by a next previous quantized code and a next previous step size but also by a reference size which is determined in accordance with an average level derived from a plurality of prior quantized codes produced until production of the next previous quantized code. A decoder decodes the quantized code succession into a reproduction of the quantizer input signal succession with each quantized code decoded with reference to a similarly adaptively decided step size. It is possible that the reference step size to be determined in a digital fashion as one of a few predetermined sizes or in an analog manner to be variable between two predetermined reference sizes. Each quantizer input signal may be given either as an analog signal sample or as a digital signal represented by a plurality of bits which are greater in number than the bits of each quantized code produced by the quantizer.
摘要翻译：提供给量化器的一系列输入信号在采样时刻被处理成一连串的量化代码，通过步长大小与参考当前步长大小相关的当前步骤大小，参考当前步骤大小，不仅由下一个先前的量化代码和下一个前一步长，而且还包括一个参考尺寸，该参考尺寸根据从直到产生下一个前一量化代码产生的多个先前量化码产生的平均水平来确定。解码器将量化代码序列解码解码为量化器输入信号继承的再现，每个量化代码参照类似的自适应决定的步长进行解码。可以以数字方式将参考步长确定为几个预定尺寸之一或以模拟方式在两个预定参考尺寸之间变化。每个量化器输入信号可以作为模拟信号采样或作为数字信号表示，该数字信号由数量大于由量化器产生的每个量化代码的位数的多个位表示。

9. 发明授权

US4835611A Timing signal generator for a video signal processor 失效
标题翻译：视频信号处理器的定时信号发生器
公开(公告)号：US4835611A
公开(公告)日：1989-05-30
申请号：US138129
申请日：1987-12-28
申请人： Takao Nishitani
发明人： Takao Nishitani
IPC分类号： H04N5/907 , G09G5/18
CPC分类号： G09G5/18
摘要： A timing signl generator for use in a multi-processor real-time digital video processing system. Each processor in the multiprocessing system is responsible for processing a selected portion of the video picture frame, as diesignated by the timing signal generator in each processor. The timing signals include a write signal instructing the receipt of the input picture block, an execution signal instructing the processing of the picture block, and an output command signal instructing the read out of the processed picture block. The timing signal generator is composed of row and column memory circuits which are respectively addressed by row and column address counters. The counters are caused to advance in response to indications that preselected coordinates in the picture frame have been reached. As inputs, the timing signal generator receives the pixel clock as well as horizontal and vertical sync signals, the former and latter of which are counted to keep track of the current coordinates. Outputs from the rwo and column memories are decoded to form the write, execute and output command signals.

10. 发明授权

US4395595A Digital pushbutton signalling receiver 失效
标题翻译：数字按钮信号接收器
公开(公告)号：US4395595A
公开(公告)日：1983-07-26
申请号：US251829
申请日：1981-04-07
申请人： Takao Nishitani , Tadaharu Kato
发明人： Takao Nishitani , Tadaharu Kato
IPC分类号： H04Q1/457 , H04M1/50
CPC分类号： H04Q1/4575
摘要： A digital pushbutton (PB) signalling receiver having reduced sampling frequency for reducing the operations required by digital filters. The PB receiver is responsive to an in-band audio signal digitized at a conventional sampling frequency (e.g., 8 KHz) and detects two PB frequencies, one from a lower group and one from a higher group of frequencies. The input signal is successively digitally filtered and sampled, with each sampling frequency being reduced by 1/2 from the preceeding sampling frequency. This results in two digitized outputs, both of which are much lower sampled digitized signals than the input, and each of which contains information corresponding to said lower and higher groups of frequencies, respectively. The two outputs are then applied to two banks of frequency detectors, comprising digital band-pass filters and energy calculating circuits, for providing an indication of the presence of the lower and higher group of frequencies in the original input signal.
摘要翻译：数字按钮（PB）信令接收机具有降低的采样频率以减少数字滤波器所需的操作。 PB接收机响应于以常规采样频率（例如，8KHz）数字化的带内音频信号，并且检测两个PB频率，一个来自较低组，一个来自较高频率组。输入信号被连续数字滤波和采样，每个采样频率从先前的采样频率减少1/2。这导致两个数字化输出，它们都比输入低得多的采样数字化信号，并且每个输出分别包含对应于所述较低和较高频率组的信息。然后，两个输出被施加到两组频率检测器，包括数字带通滤波器和能量计算电路，用于提供原始输入信号中较低和较高频率组的存在的指示。

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