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1. 发明授权

US4817047A Processing circuit capable of raising throughput of accumulation 失效
标题翻译：处理电路能够提高积累的吞吐量
公开(公告)号：US4817047A
公开(公告)日：1989-03-28
申请号：US883703
申请日：1986-07-09
申请人： Takao Nishitani , Ichiro Kuroda , Hideo Tanaka , Kyosuke Sugishita
发明人： Takao Nishitani , Ichiro Kuroda , Hideo Tanaka , Kyosuke Sugishita
IPC分类号： E04H17/14 , G06F7/38 , G06F7/544 , G06F17/10 , H03H17/02 , G06F7/52
CPC分类号： G06F7/5443 , G06F17/10 , G06F7/49921
摘要： A digital signal processing circuit reduces the occurrence of overflow conditions during successive arithmetic operations. The product output of a multiplication circuit is shifted by a barrel shifter to round off a predetermined number of least significant bits, thereby reducing the occurrence of an overflow condition when the successive product outputs of the multiplication circuit are summed by an arithmetic logic unit (ALU) to produce a summed output. The summed output is then shifted toward the most significant bit by a predetermined number before an output signal is generated. An overflow detection and correction circuit is provided in the event of an overflow condition occurring either to the ALU or the barrel shifter.
摘要翻译：数字信号处理电路在连续的算术运算期间减少了溢出状况的发生。乘法电路的乘积输出由桶形移位器移位以舍弃预定数量的最低有效位，从而当乘法电路的连续乘积输出由算术逻辑单元（ALU）相加时减少溢出状况的发生）产生一个总和输出。然后，在产生输出信号之前，将相加的输出向最高有效位移位预定数。在ALU或桶形移位器发生溢出状况的情况下，提供溢出检测和校正电路。

2. 发明申请

US20090109770A1 SEMICONDUCTOR DEVICE WITH DDR MEMORY CONTROLLER 失效
标题翻译：具有DDR存储器控制器的半导体器件
公开(公告)号：US20090109770A1
公开(公告)日：2009-04-30
申请号：US12256024
申请日：2008-10-22
申请人： Kyosuke Sugishita
发明人： Kyosuke Sugishita
IPC分类号： G11C8/18 , G11C7/00
CPC分类号： G11C8/18 , G06F13/1689 , H03L7/0805 , H03L7/0814 , Y02D10/14
摘要： In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive one of the plurality of clock signals which has a maximum frequency as a reference clock signal to determine a delay code. A slave delay circuit is configured to delay a strobe signal from the DDR memory based on the determined delay code to generate an internal strobe signal for a data signal from the DDR memory.
摘要翻译：在DDR存储器控制器中，时钟控制电路被配置为基于频率选择信号将从具有不同频率的多个时钟信号中选出的时钟信号作为操作时钟信号输出到DDR存储器。主DLL电路被配置为接收具有最大频率的多个时钟信号中的一个作为参考时钟信号以确定延迟码。从属延迟电路被配置为基于所确定的延迟码来延迟来自DDR存储器的选通信号，以产生来自DDR存储器的数据信号的内部选通信号。

3. 发明授权

US07911858B2 Semiconductor device with DDR memory controller 失效
标题翻译：具有DDR存储器控制器的半导体器件
公开(公告)号：US07911858B2
公开(公告)日：2011-03-22
申请号：US12256024
申请日：2008-10-22
申请人： Kyosuke Sugishita
发明人： Kyosuke Sugishita
IPC分类号： G11C7/00 , G11C8/02
CPC分类号： G11C8/18 , G06F13/1689 , H03L7/0805 , H03L7/0814 , Y02D10/14
摘要： In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive one of the plurality of clock signals which has a maximum frequency as a reference clock signal to determine a delay code. A slave delay circuit is configured to delay a strobe signal from the DDR memory based on the determined delay code to generate an internal strobe signal for a data signal from the DDR memory.
摘要翻译：在DDR存储器控制器中，时钟控制电路被配置为基于频率选择信号将从具有不同频率的多个时钟信号中选出的时钟信号作为操作时钟信号输出到DDR存储器。主DLL电路被配置为接收具有最大频率的多个时钟信号中的一个作为参考时钟信号以确定延迟码。从属延迟电路被配置为基于所确定的延迟码来延迟来自DDR存储器的选通信号，以产生来自DDR存储器的数据信号的内部选通信号。

4. 发明授权

US5331571A Testing and emulation of integrated circuits 失效
标题翻译：集成电路的测试和仿真
公开(公告)号：US5331571A
公开(公告)日：1994-07-19
申请号：US919417
申请日：1992-07-22
申请人： Alan P. Aronoff , Marc S. Birnkrant , Osamu Matsushima , Kyosuke Sugishita , Hisaharu Oba , Katta N. Reddy , Richard I. Olsen , Brent N. Dichter
发明人： Alan P. Aronoff , Marc S. Birnkrant , Osamu Matsushima , Kyosuke Sugishita , Hisaharu Oba , Katta N. Reddy , Richard I. Olsen , Brent N. Dichter
IPC分类号： G06F11/26 , G06F11/267 , G06G7/48 , G06F15/00
CPC分类号： G06F11/261 , G06F11/2236
摘要： An architecture is provided for testing and emulating an integrated circuit with embedded function blocks. The output nodes of the function blocks are connected through a tri-state buffer to a test bus which in turn is connected to configurable external pins. The external pins multiplex the normal I/O in normal mode and the test bus I/O in the test mode. The test bus is also connected through multiplexers to input nodes of function blocks. In test mode, the function block nodes are accessed through the test bus. For emulation of an embedded microcontroller or microprocessor, the internal connections of the microcontroller (or microprocessor) are brought out to those external pins which in normal operation are connected only to the microcontroller and not to any other function block. An in-circuit emulator (ICE) emulating the microcontroller is connected to the other function blocks through those external pins.
摘要翻译：提供了一种用于测试和仿真具有嵌入式功能块的集成电路的架构。功能块的输出节点通过三态缓冲器连接到测试总线，测试总线又连接到可配置的外部引脚。外部引脚在正常模式下复用正常I / O，并在测试模式下复用测试总线I / O。测试总线也通过多路复用器连接到功能块的输入节点。在测试模式下，通过测试总线访问功能块节点。为了仿真嵌入式微控制器或微处理器，微控制器（或微处理器）的内部连接被引出到正常操作中仅连接到微控制器而不是任何其他功能块的那些外部引脚。仿真微控制器的在线仿真器（ICE）通过这些外部引脚连接到其他功能块。

5. 发明申请

US20110141834A1 SEMICONDUCTOR DEVICE WITH DDR MEMORY CONTROLLER 审中-公开
标题翻译：具有DDR存储器控制器的半导体器件
公开(公告)号：US20110141834A1
公开(公告)日：2011-06-16
申请号：US13035209
申请日：2011-02-25
申请人： Kyosuke SUGISHITA
发明人： Kyosuke SUGISHITA
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G06F13/1689 , H03L7/0805 , H03L7/0814 , Y02D10/14
摘要： In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive one of the plurality of clock signals which has a maximum frequency as a reference clock signal to determine a delay code. A slave delay circuit is configured to delay a strobe signal from the DDR memory based on the determined delay code to generate an internal strobe signal for a data signal from the DDR memory.
摘要翻译：在DDR存储器控制器中，时钟控制电路被配置为基于频率选择信号将从具有不同频率的多个时钟信号中选出的时钟信号作为操作时钟信号输出到DDR存储器。主DLL电路被配置为接收具有最大频率的多个时钟信号中的一个作为参考时钟信号以确定延迟码。从属延迟电路被配置为基于所确定的延迟码来延迟来自DDR存储器的选通信号，以产生来自DDR存储器的数据信号的内部选通信号。

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