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1. 发明授权

US4825361A Vector processor for reordering vector data during transfer from main memory to vector registers 失效
标题翻译：向量处理器，用于在从主存储器传送到向量寄存器时重新排列向量数据
公开(公告)号：US4825361A
公开(公告)日：1989-04-25
申请号：US21590
申请日：1987-03-02
申请人： Koichiro Omoda , Shunichi Torii , Shigeo Nagashima , Yasuhiro Inagami , Takayuki Nakagawa
发明人： Koichiro Omoda , Shunichi Torii , Shigeo Nagashima , Yasuhiro Inagami , Takayuki Nakagawa
IPC分类号： G06F17/16 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8076
摘要： A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.
摘要翻译：一种矢量处理器，具有由12位字节大小的元素构成的向量寄存器，用于存储由从具有多个存储区域的主存储器读出的多个元素组成的矢量数据，并且能够读出l1- 字节大小从指定的地址限制开始，并适用于顺序地向向量寄存器中写入具有m（l1 / m为整数，l2大于或等于m）的元素大小的向量数据，从向量寄存器，用于由算术单元计算，并将计算结果写入向量寄存器，其中处理器以从后续操作所需的顺序将从主存储器读出的向量数据的元素写入分离的向量寄存器的指定位置。

2. 发明授权

US4910667A Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit 失效
标题翻译：矢量处理器，带矢量缓冲存储器，用于在矢量存储和操作单元之间读取或写入矢量数据
公开(公告)号：US4910667A
公开(公告)日：1990-03-20
申请号：US184788
申请日：1988-04-22
申请人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
发明人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
IPC分类号： G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8053
摘要： In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.
摘要翻译：在具有向量寄存器的向量处理器中，用于临时存储向量数据的向量缓冲存储器比向主存储器靠近向量寄存器布置，并且向量缓冲器存储控制包括用于存储存储在提供缓冲存储器的存储位置和用于检查矢量数据识别信息是否在识别存储器中的检查电路。向量缓冲存储控制检查由主存储器的矢量数据获取指令指定的矢量数据的识别信息是否在识别存储器中，并且如果它在识别存储器中，则从缓冲存储器中取出向量数据，将其传送到向量寄存器，如果不在识别存储器中，则指示从主存储器获取向量数据，将从主存储器获取的向量数据传送到向量寄存器，并将其存储到缓冲存储器中。

3. 发明授权

US4782441A Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions 失效
标题翻译：能够平行执行指令并保留执行状态顺序的矢量处理器重新启动中断的执行
公开(公告)号：US4782441A
公开(公告)日：1988-11-01
申请号：US872396
申请日：1986-06-10
申请人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
发明人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F15/78 , G06F17/16 , G06F9/28 , G06F7/00
CPC分类号： G06F15/8053
摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.
摘要翻译：在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。存储的信息用于在适当的点重新启动中断的程序的执行。

4. 发明授权

US4899273A Circuit simulation method with clock event suppression for debugging LSI circuits 失效
标题翻译：用于调试LSI电路的时钟事件抑制的电路仿真方法
公开(公告)号：US4899273A
公开(公告)日：1990-02-06
申请号：US940539
申请日：1986-12-10
申请人： Koichiro Omoda , Shunsuke Miyamoto , Takayuki Nakagawa , Yoshio Takamine , Shigeo Nagashima , Masayuki Miyoshi , Yoshiharu Kazama , Yoshiaki Kinoshita
发明人： Koichiro Omoda , Shunsuke Miyamoto , Takayuki Nakagawa , Yoshio Takamine , Shigeo Nagashima , Masayuki Miyoshi , Yoshiharu Kazama , Yoshiaki Kinoshita
IPC分类号： G06F17/16 , G01R31/317 , G01R31/3173 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5022 , G01R31/31705 , G01R31/3173
摘要： A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.
摘要翻译：一种用于检查大规模逻辑电路的逻辑运算的计算机实现的逻辑模拟方法，计算时钟同步逻辑电路中至少一个锁存器的输出的变化。时钟同步逻辑电路包含组合逻辑电路和多个逻辑门。每个逻辑门具有至少一个输入信号和几个其他输入，其连接到不同相位的时钟信号源。锁存器由用于保持组合逻辑电路的输出的时钟信号的上升或下降而被激活。因此，该方法实现了输出的采样时刻，以确定大规模电路的逻辑运算。

5. 发明授权

US4881168A Vector processor with vector data compression/expansion capability 失效
标题翻译：矢量处理器具有矢量数据压缩/扩展能力
公开(公告)号：US4881168A
公开(公告)日：1989-11-14
申请号：US034950
申请日：1987-04-06
申请人： Yasuhiro Inagami , Takayuki Nakagawa , Yoshiko Tamaki , Shigeo Nagashima
发明人： Yasuhiro Inagami , Takayuki Nakagawa , Yoshiko Tamaki , Shigeo Nagashima
IPC分类号： G06F17/16 , G06F15/78 , G06T9/00
CPC分类号： G06F9/3824 , G06F15/8084 , G06F9/30043 , G06T9/008
摘要： A vector processor has a memory for storing vector data, a plurality of vector registers each capable of reading or writing plural (m) vector elements in parallel, at least one mask vector register capable of storing m mask bits in parallel, and a transfer section connected to the memory, the plurality of vector registers and the mask vector register and responsive to a store compression instruction or a load expansion instruction for transferring vector elements to or from regularly spaced address locations within the memory from or to selected storage locations of a selected vector register corresponding to valid mask bits. The transfer section includes at least one count unit connected to the mask vector register for counting a total number of valid mask bits within all of the already read out mask bits, and plural (m) access units operable concurrently and connected to the count unit and the mask vector register. Each access unit is responsive to the validity of a corresponding one within currently read out m mask bits, to a total number of valid mask bits or invalid mask bits included within the currently read m mask bits and having preceding sequential numbers of elements to that of the corresponding mask bit, and to the counted total number, and operates to generate an address of a location within the memory which holds a vector element to be transferred to a storage location corresponding to the corresponding mask bit within the selected vector register or which should receive a vector element read out from the storage location.
摘要翻译：矢量处理器具有用于存储矢量数据的存储器，能够并行地读取或写入多个（m）个矢量元素的多个矢量寄存器，能够并行存储m个掩码位的至少一个掩码向量寄存器，以及传送部分连接到存储器，多个向量寄存器和掩码向量寄存器，并且响应于存储器压缩指令或负载扩展指令，用于将存储器内的规则间隔地址位置中的向量元素传送到所选择的存储器或选定的存储位置向量寄存器对应于有效的掩码位。传送部分包括至少一个计数单元，连接到掩模向量寄存器，用于对所有已经读出的掩码位内的有效掩码位的总数进行计数;以及多个（m）个访问单元，可同时并行连接到计数单元，掩码向量寄存器。每个访问单元响应于当前读出的m个掩码位内的对应的有效值，到当前读取的m个掩码位内包括的有效屏蔽位或无效掩码位的总数，并且具有先前的顺序数目的元素对应的屏蔽位和计数的总数，并且操作以产生存储器内的位置的地址，该地址保存要传送到与所选择的向量寄存器内的对应掩码位相对应的存储位置的向量元素，或者应当接收从存储位置读出的向量元素。

6. 发明授权

US4803620A Multi-processor system responsive to pause and pause clearing instructions for instruction execution control 失效
标题翻译：响应暂停和暂停清除指令执行控制指令的多处理器系统
公开(公告)号：US4803620A
公开(公告)日：1989-02-07
申请号：US445
申请日：1987-01-05
申请人： Yasuhiro Inagami , Takayuki Nakagawa , Shigeo Nagashima
发明人： Yasuhiro Inagami , Takayuki Nakagawa , Shigeo Nagashima
IPC分类号： G06F15/16 , G06F9/38 , G06F9/52 , G06F15/163 , G06F15/177 , G06F15/78 , G06F17/16 , G06F9/30
CPC分类号： G06F15/8076 , G06F9/30036 , G06F9/3877
摘要： A multi-processor system including a main storage for storing instructions and data, a master processor for supplying to a slave processor data required for the processing to be executed by the slave processor and commanding initiation of the processing, the master processor further operating to test the operation state of the slave processor and perform processing by utilizing the result of the processing executed by the slave processor. The slave processor initiates the processing under the command of the master processor and operates to inform of the master processor of completion of the processing. The slave processor operates to execute a pause instruction for suspending temporarily activation of processing for a succeeding instruction and setting a pause indication at an indicator of the slave processor. When the pause indication is set in the slave processor, the master processor operates to reset this indication to release the slave processor from the pause state. When the pause state indication is not set, the master processor executes a clearing instruction supplied from the main storage for suspending the function to activate the succeeding instruction. The slave processor also operates to set at the indicator an indication instruction indicating completion of execution of the succedding instruction. The master processor functions to reset the indication of completed execution of instruction set at the slave processor and otherwise execute an indication resetting instruction for suspending activation of a succeeding instruction.
摘要翻译：一种多处理器系统，包括用于存储指令和数据的主存储器，用于向从处理器提供由从处理器执行的处理所需的数据的主处理器以及命令启动处理，主处理器进一步操作以测试从属处理器的操作状态，并利用从属处理器执行的处理结果来执行处理。从处理器在主处理器的命令下启动处理，并且操作以通知主处理器完成处理。从处理器操作以执行暂停指令，暂停对后续指令的处理的暂时激活，并在从属处理器的指示器处设置暂停指示。当在从属处理器中设置暂停指示时，主处理器操作以复位该指示，以使从属处理器从暂停状态释放。当暂停状态指示未设置时，主处理器执行从主存储器提供的清除指令，以暂停用于激活后续指令的功能。从处理器还用于在指示器处设置指示完成执行完成指令的指示。主处理器用于重置在从属处理器处的指令集的完成执行的指示，否则执行用于暂停后续指令的激活的指示复位指令。

7. 发明授权

US4773006A Vector operation designator 失效
标题翻译：矢量操作指示器
公开(公告)号：US4773006A
公开(公告)日：1988-09-20
申请号：US813007
申请日：1985-12-24
申请人： Yoshiaki Kinoshita , Yoshiharu Kazama , Shunsuke Miyamoto , Koichiro Omoda , Takayuki Nakagawa
发明人： Yoshiaki Kinoshita , Yoshiharu Kazama , Shunsuke Miyamoto , Koichiro Omoda , Takayuki Nakagawa
IPC分类号： G06F17/16 , G06F15/78 , G06F7/48 , G06F3/00
CPC分类号： G06F15/8053
摘要： In a vector processor for performing an operation on first and second vectors for each vector element, an operation code is set for each vector element of at least one of the first and second vectors to designate the type of an operation to be executed on the vector element, and the operation is carried out on the first and second vectors for each vector element based on the operation code.
摘要翻译：在用于对每个向量元素执行对第一和第二向量的操作的向量处理器中，为第一和第二向量中的至少一个矢量的每个矢量元素设置操作码，以指定要在矢量上执行的操作的类型元素，并且基于操作代码对每个向量元素的第一和第二向量执行操作。

8. 发明授权

US4792893A Selectively recursive pipelined parallel vector logical operation system 失效
标题翻译：选择性递归流水线并行向量逻辑运算系统
公开(公告)号：US4792893A
公开(公告)日：1988-12-20
申请号：US782534
申请日：1985-10-01
申请人： Takayuki Nakagawa , Koichiro Omoda
发明人： Takayuki Nakagawa , Koichiro Omoda
IPC分类号： G06F17/16 , G06F7/00 , G06F15/78 , G06F7/48
CPC分类号： G06F15/8084 , G06F7/00
摘要： A vector logical operation apparatus includes first and second registers respectively for sequentially receiving first and second sets of vector elements which first and second sets of vector elements are supplied in pairs on the same sequential clock periods; third register; a plurality of first gates connected to the first and third registers each for performing a first bitwise logical operation on bit signals partly provided from the first register and the third register; a plurality of second gates connected to the second register and the first gates in a bitwise manner each for performing a second bitwise logical operation on bit signals provided from the second register and the first gates; a feed back circuit connected to the plurality of second gates for supplying the outputs of the second gates to the third register; and control circuit connected to the third register for ordering the third register to receive an applied initial data signal on or before supply of a pair of the first vector element of the first set and second set and to repeatedly receive the outputs of the second gates provided by the feed back circuit on sequential clock periods each clock period being one clock period later after receipt a pair of vector elements by the first and second registers; wherein the first and second gates are operable fast enough so that the outputs of the second gates at the end of each clock period fully responds to vector elements held by the first to third registers at the beginning of each clock period.
摘要翻译：矢量逻辑运算装置分别包括第一和第二寄存器，用于顺序地接收第一和第二组向量元素，第一和第二组矢量元素在相同的顺序时钟周期上成对提供; 第三个登记册连接到第一和第三寄存器的多个第一门，用于对从第一寄存器和第三寄存器部分提供的位信号执行第一按位逻辑运算; 多个第二栅极，以逐位方式连接到第二寄存器和第一门，每个用于对从第二寄存器和第一门提供的位信号执行第二按位逻辑运算; 连接到所述多个第二栅极的反馈电路，用于将所述第二栅极的输出提供给所述第三寄存器; 以及连接到第三寄存器的控制电路，用于对第三寄存器进行排序，以在第一组和第二组的一对第一向量元素的供给之前或之前接收所施加的初始数据信号，并重复地接收提供的第二门的输出通过在顺序时钟周期上的反馈电路，每个时钟周期是在由第一和第二寄存器接收到一对向量元素之后的一个时钟周期内; 其中第一和第二门可操作得足够快，使得在每个时钟周期结束时，第二门的输出在每个时钟周期的开始处完全响应由第一至第三寄存器保持的向量元素。

9. 发明授权

US09463520B2 Wire electric discharge machining apparatus and control device 有权
标题翻译：线放电加工装置及控制装置
公开(公告)号：US09463520B2
公开(公告)日：2016-10-11
申请号：US13979928
申请日：2012-10-30
申请人： Hiroshi Sugie , Hiroyuki Takeda , Takayuki Nakagawa
发明人： Hiroshi Sugie , Hiroyuki Takeda , Takayuki Nakagawa
IPC分类号： B23H7/10 , B23H7/06
CPC分类号： B23H7/065 , B23H7/10 , B23H7/105
摘要： The present invention includes drive units 7a and 7b that change a relative position between a wire electrode 12 and a workpiece 14 by moving a position of wire guide 8a and 8b, drive control units 6a and 6b that drive the drive units 7a and 7b based on a machining shape on the workpiece 14, respectively, a correction-amount storage unit 3 that previously stores therein a position correction amount for the wire electrode 12 corresponding to a machining condition, a correction-amount reading unit 4 that reads the position correction amount corresponding to the machining condition from the correction-amount storage unit 3, and a wire-position correction unit 5 that causes the drive control units 6a and 6b to correct a relative distance between the wire electrode 12 and the workpiece 14 based on the read position correction amount.
摘要翻译：本发明包括通过移动导线器8a和8b的位置来改变线电极12和工件14之间的相对位置的驱动单元7a和7b，基于驱动单元7a和7b驱动驱动单元7a和7b的驱动控制单元6a和6b 工件14上的加工形状，分别预先存储有对应于加工条件的线电极12的位置校正量的校正量存储单元3，读取对应于位置校正量的校正量读取单元4 以及线位置校正单元5，其使驱动控制单元6a和6b基于读取位置校正来校正线电极12和工件14之间的相对距离。量。

10. 发明授权

US08664559B2 Electrical discharge machine 有权
标题翻译：放电机
公开(公告)号：US08664559B2
公开(公告)日：2014-03-04
申请号：US11816830
申请日：2005-02-28
申请人： Hidetaka Miyake , Takayuki Nakagawa , Yoshihito Imai
发明人： Hidetaka Miyake , Takayuki Nakagawa , Yoshihito Imai
IPC分类号： B23H7/26
CPC分类号： B23H9/14 , B23H7/265 , B23H2400/10
摘要： An electrical discharge machine feeds an electrode wire received within a guide tube to a process region of a machined article. The electrical discharge machine includes a cylindrical hollow driving shaft arranged in a vertical direction, which has a space for receiving the guide tube with the electrode wire along a vertical central axis. A head assembly includes a first holding member for holding the guide tube, and a second holding member for holding the electrode wire extending from a bottom opening of the guide tube. The head assembly is detachably coupled with a bottom portion of the driving shaft. Therefore, the electrode wire can be replaced by replacing the head assembly.
摘要翻译：放电机器将接收在引导管内的电极丝馈送到加工制品的加工区域。放电机包括沿垂直方向布置的圆柱形中空驱动轴，其具有用于沿垂直中心轴线接收具有电极线的引导管的空间。头组件包括用于保持引导管的第一保持构件和用于保持从引导管的底部开口延伸的电极线的第二保持构件。头部组件与驱动轴的底部可拆卸地联接。因此，可以通过更换头部组件来代替电极线。

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