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1. 发明授权

US08514627B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08514627B2
公开(公告)日：2013-08-20
申请号：US13235389
申请日：2011-09-18
申请人： Kiyotaro Itagaki , Masaru Kito , Ryu Ogiwara , Hitoshi Iwai
发明人： Kiyotaro Itagaki , Masaru Kito , Ryu Ogiwara , Hitoshi Iwai
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/344 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
摘要翻译：控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。

2. 发明申请

US20120069663A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120069663A1
公开(公告)日：2012-03-22
申请号：US13235389
申请日：2011-09-18
申请人： Kiyotaro ITAGAKI , Masaru Kito , Ryu Ogiwara , Hitoshi Iwai
发明人： Kiyotaro ITAGAKI , Masaru Kito , Ryu Ogiwara , Hitoshi Iwai
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/344 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
摘要翻译：控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。

3. 发明授权

US08531901B2 Three dimensional NAND type memory device having selective charge pump activation to minimize noise 有权
标题翻译：具有选择性电荷泵激活以使噪声最小化的三维NAND型存储器件
公开(公告)号：US08531901B2
公开(公告)日：2013-09-10
申请号：US13196417
申请日：2011-08-02
申请人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
发明人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
IPC分类号： G11C7/02
CPC分类号： G11C16/30 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.
摘要翻译：半导体存储器件包括单元阵列，电压产生电路和控制电路。单元阵列包括存储单元串。电压产生电路布置在电池阵列的下方。每个存储单元串包括半导体层，控制栅极和存储单元晶体管。半导体层包括一对柱部和连接部。控制门与柱部相交。存储单元晶体管形成在柱部分和控制栅极的交点处。在写入操作和读取操作中，控制电路不驱动对作为写入目标和读取目标的存储单元串产生噪声的电压产生电路，并且驱动不对存储器单元串产生噪声的电压产生电路作为写目标和读目标。

4. 发明申请

US20120057405A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120057405A1
公开(公告)日：2012-03-08
申请号：US13196417
申请日：2011-08-02
申请人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
发明人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/30 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.
摘要翻译：根据一个实施例，半导体存储器件包括单元阵列，电压产生电路和控制电路。单元阵列包括存储单元串。电压产生电路布置在电池阵列的下方。每个存储单元串包括半导体层，控制栅极和存储单元晶体管。半导体层包括一对柱部和连接部。控制门与柱部相交。存储单元晶体管形成在柱部分和控制栅极的交点处。在写入操作和读取操作中，控制电路不驱动对作为写入目标和读取目标的存储单元串产生噪声的电压产生电路，并且驱动不对存储器单元串产生噪声的电压产生电路作为写目标和读目标。

5. 发明授权

US08760924B2 Nonvolatile semiconductor memory device and method of data write therein 有权
标题翻译：非易失性半导体存储器件及其中的数据写入方法
公开(公告)号：US08760924B2
公开(公告)日：2014-06-24
申请号：US13427263
申请日：2012-03-22
申请人： Hitoshi Iwai , Tomoko Fujiwara , Hideaki Aochi , Masaru Kito
发明人： Hitoshi Iwai , Tomoko Fujiwara , Hideaki Aochi , Masaru Kito
IPC分类号： G11C16/04
CPC分类号： G11C16/3454 , G11C16/0483 , G11C16/06
摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.
摘要翻译：存储单元包括第一半导体层和第一导电层。第一半导体层相对于半导体衬底在垂直方向上延伸。第一导电层与第一半导体层夹着电荷存储层。控制电路执行第一程序操作，然后执行第二程序操作。第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。

6. 发明申请

US20060221729A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060221729A1
公开(公告)日：2006-10-05
申请号：US11194539
申请日：2005-08-02
申请人： Hitoshi Iwai , Shinji Miyano
发明人： Hitoshi Iwai , Shinji Miyano
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0405 , G11C2029/1208 , G11C2229/743 , G11C2229/746 , G11C2229/763 , G11C2229/766
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a plurality of redundancy sections respectively provided for the plurality of memory blocks and configured to be substituted for defective memory cells, a test circuit that carries out a test on the memory cell array and outputs defective data, first and second memory circuit that temporarily store the defective data, a first write circuit that writes the defective data alternately in the first and second memory circuits, a first read circuit that reads the defective data alternately from the first and second memory circuits, a plurality of third memory circuits respectively provided for the plurality of memory blocks, that store the defective data, and a second write circuit that writes defective data read by the first read circuit in a third memory circuit corresponding to a memory block in which an error occurred.
摘要翻译：一种半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，多个冗余部分，分别为多个存储器块提供并被配置为代替有缺陷的存储器单元;测试电路，对存储器进行测试单元阵列并输出缺陷数据，临时存储缺陷数据的第一和第二存储器电路，将缺陷数据交替地写入第一和第二存储器电路的第一写入电路，从第一个存储器电路交替读取缺陷数据的第一读取电路和第二存储器电路，分别为存储有缺陷数据的多个存储器块提供的多个第三存储器电路;以及第二写入电路，其将由第一读取电路读取的缺陷数据写入与存储器相对应的第三存储器电路中阻塞发生错误。

7. 发明申请

US20060090954A1 Steering system and method of control 失效
公开(公告)号：US20060090954A1
公开(公告)日：2006-05-04
申请号：US11265606
申请日：2005-11-02
申请人： Nobuo Sugitani , Yoshimitsu Akuta , Hisao Asaumi , Hitoshi Iwai , Masaaki Kawano , Takashi Nishimori
发明人： Nobuo Sugitani , Yoshimitsu Akuta , Hisao Asaumi , Hitoshi Iwai , Masaaki Kawano , Takashi Nishimori
IPC分类号： B62D5/04
CPC分类号： B62D5/003 , B62D5/006 , B62D5/0496
摘要： A steering system includes a steering wheel, a steering angle sensor detecting a steering angle, a steering motor steering road-wheels, a reaction motor imparting a reaction force to the steering wheel, an ECU driving the steering motor with respect to a detected steering angle and a temperature detecting unit detecting temperatures of the steering motor, the reaction motor or a constituent member involved in the temperatures of the motors. When the temperature detected is larger than a predetermined value, the ECU performs such that a ratio of the rotating angle to the steering angle is made smaller than one that is to result when the temperature is equal to or smaller than the predetermined value, or a reaction force that is to be imparted to the steering wheel is made larger.

8. 发明申请

US20050224276A1 Steering device 有权
标题翻译：转向装置
公开(公告)号：US20050224276A1
公开(公告)日：2005-10-13
申请号：US11099070
申请日：2005-04-05
申请人： Nobuo Sugitani , Hitoshi Iwai
发明人： Nobuo Sugitani , Hitoshi Iwai
IPC分类号： B62D5/00 , B62D5/04 , B62D5/06 , B62D6/00 , B62D101/00 , B62D113/00 , B62D119/00
CPC分类号： B62D6/008
摘要： A steering device in which a steering wheel which a driver operates and wheels which are steered are not mechanically connected has a target turning angle determination device which determines a target turning angle of the wheels according to an operation amount of the steering wheel, a turning angle sensor which measures an actual turning angle of the wheels, a steering motor which turns the wheels according to a deviation between the target turning angle and the actual turning angle, a target steering reaction force setting section which determines a steering reaction force to be applied to the steering wheel, and a steering reaction force motor which applies the steering reaction force, in which a rate of increase of the steering reaction force is raised when the actual turning angle approaches a maximum turning angle.
摘要翻译：一种转向装置，其中驾驶员操作的方向盘和被转向的车轮没有机械连接，所述转向装置具有根据所述方向盘的操作量确定所述车轮的目标转动角度的转向角确定装置，传感器，其测量车轮的实际转动角度;转向电动机，其根据目标转向角度与实际转弯角度之间的偏差转动车轮;目标转向反作用力设定部件，其确定要施加到的转向反作用力方向盘和转向反作用力马达，该转向反作用力马达施加转向反作用力，其中当实际转向角接近最大转向角时转向反作用力的增加率升高。

9. 发明授权

US08315097B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08315097B2
公开(公告)日：2012-11-20
申请号：US13026616
申请日：2011-02-14
申请人： Tomoo Hishida , Hitoshi Iwai , Yoshihisa Iwata
发明人： Tomoo Hishida , Hitoshi Iwai , Yoshihisa Iwata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , H01L27/11582
摘要： A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.
摘要翻译：存储器串由多个存储晶体管和备用存储晶体管串联连接。字线连接到存储晶体管的栅极。备用字线连接到备用存储晶体管的栅极。存储器串包括第一半导体层，电荷存储层，多个第一导电层和第二导电层。第一半导体层相对于基板在垂直方向上延伸。电荷存储层包围第一半导体层的侧表面。多个第一导电层围绕第一半导体层的侧表面，电荷存储层位于其间，并用作字线。第二导电层围绕第一半导体层的侧表面，电荷存储层位于其间，用作备用字线。

10. 发明申请

US20120269551A1 OPTICAL SCANNING APPARATUS AND IMAGE FORMING APPARATUS INCLUDING OPTICAL SCANNING APPARATUS 有权
标题翻译：光学扫描装置和图像形成装置，包括光学扫描装置
公开(公告)号：US20120269551A1
公开(公告)日：2012-10-25
申请号：US13437300
申请日：2012-04-02
申请人： Hitoshi Iwai
发明人： Hitoshi Iwai
IPC分类号： G03G15/04 , G02B26/10
CPC分类号： G03G15/04045 , G03G21/1666
摘要： At the time of forming an image, a rise in a temperature of a drive motor generates distortion in a bottom of a optical box of an optical scanning apparatus. If an opening is formed on the optical box to release heat, the optical box becomes easily distorted. To solve such a problem, according to the present invention, the optical scanning apparatus includes a rib which crosses over the opening formed at the bottom of the optical box.
摘要翻译：在形成图像时，驱动电动机的温度上升产生光学扫描装置的光学盒的底部的变形。如果在光学盒上形成开口以释放热量，则光学盒变得容易变形。为了解决这个问题，根据本发明，光学扫描装置包括在形成在光学盒的底部的开口上的肋。

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