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1. 发明授权

US08873330B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08873330B2
公开(公告)日：2014-10-28
申请号：US13417503
申请日：2012-03-12
申请人： Fumihiro Kono , Kiyotaro Itagaki
发明人： Fumihiro Kono , Kiyotaro Itagaki
IPC分类号： G11C8/00 , G06F13/16 , G11C16/08 , G11C16/04
CPC分类号： G11C16/08 , G06F13/1694 , G11C16/0483
摘要： A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.
摘要翻译：分别为存储器核提供多个地址转换电路，并将从外部提供的逻辑地址数据转换为物理地址数据。在交错操作中，地址转换电路输出逻辑地址数据作为物理地址数据，而不需要在比第二存储器核心更先访问第一存储器核心时转换逻辑地址数据，而输出地址数据作为物理地址数据的逻辑地址数据的值作为第一存储器核心的第二存储器核心的存取时间。

2. 发明授权

US08531901B2 Three dimensional NAND type memory device having selective charge pump activation to minimize noise 有权
标题翻译：具有选择性电荷泵激活以使噪声最小化的三维NAND型存储器件
公开(公告)号：US08531901B2
公开(公告)日：2013-09-10
申请号：US13196417
申请日：2011-08-02
申请人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
发明人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
IPC分类号： G11C7/02
CPC分类号： G11C16/30 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.
摘要翻译：半导体存储器件包括单元阵列，电压产生电路和控制电路。单元阵列包括存储单元串。电压产生电路布置在电池阵列的下方。每个存储单元串包括半导体层，控制栅极和存储单元晶体管。半导体层包括一对柱部和连接部。控制门与柱部相交。存储单元晶体管形成在柱部分和控制栅极的交点处。在写入操作和读取操作中，控制电路不驱动对作为写入目标和读取目标的存储单元串产生噪声的电压产生电路，并且驱动不对存储器单元串产生噪声的电压产生电路作为写目标和读目标。

3. 发明授权

US08514627B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08514627B2
公开(公告)日：2013-08-20
申请号：US13235389
申请日：2011-09-18
申请人： Kiyotaro Itagaki , Masaru Kito , Ryu Ogiwara , Hitoshi Iwai
发明人： Kiyotaro Itagaki , Masaru Kito , Ryu Ogiwara , Hitoshi Iwai
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/344 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
摘要翻译：控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。

4. 发明申请

US20120057405A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120057405A1
公开(公告)日：2012-03-08
申请号：US13196417
申请日：2011-08-02
申请人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
发明人： Ryu Ogiwara , Hitoshi Iwai , Kiyotaro Itagaki
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/30 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.
摘要翻译：根据一个实施例，半导体存储器件包括单元阵列，电压产生电路和控制电路。单元阵列包括存储单元串。电压产生电路布置在电池阵列的下方。每个存储单元串包括半导体层，控制栅极和存储单元晶体管。半导体层包括一对柱部和连接部。控制门与柱部相交。存储单元晶体管形成在柱部分和控制栅极的交点处。在写入操作和读取操作中，控制电路不驱动对作为写入目标和读取目标的存储单元串产生噪声的电压产生电路，并且驱动不对存储器单元串产生噪声的电压产生电路作为写目标和读目标。

5. 发明申请

US20110175159A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110175159A1
公开(公告)日：2011-07-21
申请号：US13120987
申请日：2009-08-25
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n
摘要翻译：每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。对于每个存储块，存储器串按第二方向布置有m列。布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。满足式（1）所示的关系：（式1）m> = n

6. 发明申请

US20070206406A1 SPIN INJECTION WRITE TYPE MAGNETIC MEMORY DEVICE 有权
标题翻译：旋转注射式磁性记忆装置
公开(公告)号：US20070206406A1
公开(公告)日：2007-09-06
申请号：US11673241
申请日：2007-02-09
申请人： Yoshihiro Ueda , Kenji Tsuchida , Tsuneo Inaba , Kiyotaro Itagaki
发明人： Yoshihiro Ueda , Kenji Tsuchida , Tsuneo Inaba , Kiyotaro Itagaki
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , Y10S977/935
摘要： A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.
摘要翻译：自旋注入写入型磁存储器件包括具有磁阻效应元件和选择晶体管的存储单元。磁阻效应元件的一端连接到第一节点。选择晶体管具有连接到磁阻效应元件的另一端的第一扩散区域和连接到第二节点的第二扩散区域。选择线沿着第一方向延伸并连接到选择晶体管的栅电极。第一互连沿着第二方向延伸并连接到第一节点。第二互连沿着第二方向延伸并且连接到第二节点。沿着第一方向相邻的两个存储单元共享第一节点。沿着第二方向相邻的两个存储单元共享第二节点。

7. 发明授权

US09036411B2 Nonvolatile semiconductor memory device and data erase method thereof 有权
标题翻译：非易失性半导体存储器件及其数据擦除方法
公开(公告)号：US09036411B2
公开(公告)日：2015-05-19
申请号：US13483610
申请日：2012-05-30
申请人： Kiyotaro Itagaki
发明人： Kiyotaro Itagaki
IPC分类号： G11C11/34 , G11C16/14 , G11C16/08 , G11C16/04 , G11C16/32
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/32
摘要： A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.
摘要翻译：根据一个方面的非易失性半导体存储器件包括半导体衬底，存储单元阵列，存储器串，漏极侧选择晶体管，源极侧选择晶体管，字线，位线，源极线，漏极侧选择栅极线，源极选择栅极线和控制电路。控制电路对所选择的位线施加第一电压，从而对连接到所选位线的所选择的存储器串执行擦除操作，并且控制电路将第二电压施加到未选择的位线，从而禁止擦除连接到未选位线的所选存储器串的操作。第一电压大于第二电压。

8. 发明授权

US08817538B2 Nonvolatile semiconductor memory device and method for erasing data thereof 有权
标题翻译：非易失性半导体存储器件及其数据的擦除方法
公开(公告)号：US08817538B2
公开(公告)日：2014-08-26
申请号：US13493370
申请日：2012-06-11
申请人： Kiyotaro Itagaki , Kunihiro Yamada , Yoshihisa Iwata
发明人： Kiyotaro Itagaki , Kunihiro Yamada , Yoshihisa Iwata
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C2213/71 , H01L27/11582 , H01L29/7926
摘要： A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.
摘要翻译：控制电路被配置为将连接到所选择的存储器串的漏极侧选择晶体管和源极侧选择晶体管设置为非导通状态。控制电路被配置为对连接到所选择的存储器串中未选择的存储器单元的栅极的未选择字线施加第一电压。控制电路被配置为对连接到所选择的存储器串中所选择的存储器单元的栅极的选定字线施加第二电压。在擦除操作中第二电压小于第一电压。

9. 发明授权

US08767466B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08767466B2
公开(公告)日：2014-07-01
申请号：US13419953
申请日：2012-03-14
申请人： Norichika Asaoka , Masanobu Shirakawa , Kiyotaro Itagaki
发明人： Norichika Asaoka , Masanobu Shirakawa , Kiyotaro Itagaki
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/1157 , H01L27/11582
摘要： When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.
摘要翻译：当执行数据擦除操作时，控制电路至少在漏极侧选择晶体管和源极侧选择晶体管中的任何一个处产生正空穴，并且将正空穴提供给存储器体的主体以提高主体的电压的存储器串到第一电压。然后，在第一时间段期间，将多个字线中的第一电压小于第一电压的电压施加到第一字线。此外，在第二时间段期间，它将小于第一电压的电压施加到与第一字线不同的第二字线。第二时间段与第一时间段不同。

10. 发明授权

US08605508B2 Non-volatile semiconductor storage device having control circuit to control voltages to select transistor for erase operation 有权
标题翻译：具有控制电路以控制电压以选择用于擦除操作的晶体管的非易失性半导体存储装置
公开(公告)号：US08605508B2
公开(公告)日：2013-12-10
申请号：US13463889
申请日：2012-05-04
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30
摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
摘要翻译：非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。一定的电位差是导致GIDL电流的电位差。

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