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1. 发明授权

US07712007B2 Semiconductor memory device having data holding mode using ECC function 失效
标题翻译：具有使用ECC功能的数据保持模式的半导体存储器件
公开(公告)号：US07712007B2
公开(公告)日：2010-05-04
申请号：US11531895
申请日：2006-09-14
申请人： Takeshi Nagai , Shinji Miyano
发明人： Takeshi Nagai , Shinji Miyano
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G11C2029/0411
摘要： When memory cells enter an operation mode which performs only data holding, a control circuit controls the memory cells and an ECC circuit as follows. A plurality of data are read out to generate and store a check bit for error detection and correction. Refreshing is performed in a period within the error occurrence allowable range of an error correcting operation performed by the ECC circuit by using the check bit. Before a normal operation mode is restored from the operation mode which performs only data holding, an error bit of the data is corrected by using the check bit. In an entry/exit period, read/write and an ECC operation are sequentially performed for all the memory cells by a page mode operation. Memory cells connected to a word line which is not accessed by the page mode operation are sequentially activated and refreshed.
摘要翻译：当存储单元进入仅执行数据保持的操作模式时，控制电路如下控制存储单元和ECC电路。读取多个数据以生成并存储用于错误检测和校正的校验位。通过使用校验位，在由ECC电路执行的纠错操作的误差发生允许范围内的时间段内进行刷新。在仅执行数据保持的操作模式恢复正常操作模式之前，通过使用校验位来校正数据的错误位。在入口/出口期间，通过页面模式操作对所有存储器单元顺序执行读/写和ECC操作。连接到不被页模式操作访问的字线的存储单元被依次激活和刷新。

2. 发明授权

US07464320B2 Synchronous semiconductor storage device having error correction function 失效
标题翻译：具有纠错功能的同步半导体存储装置
公开(公告)号：US07464320B2
公开(公告)日：2008-12-09
申请号：US11274402
申请日：2005-11-16
申请人： Takeshi Nagai , Shinji Miyano
发明人： Takeshi Nagai , Shinji Miyano
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C7/1039 , G11C7/1072 , G11C11/4093 , G11C11/4096 , G11C2029/0411 , G11C2207/104
摘要： A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines. The write operation allows the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines. Further, in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.
摘要翻译：半导体存储器件具有其中布置多个存储器单元并与时钟信号同步操作的存储单元阵列。在同一周期的时钟信号中执行读写操作。读操作允许由第一列地址指定的读列选择线将读数据总线连接到位线。写操作允许由第二列地址指定的写列选择线将写数据总线连接到位线。此外，在写入操作中，通过将由校正子产生电路和校正电路进行了纠错的数据与输入到输入电路的数据组合而获得的数据由代码生成电路编码并写入记忆细胞

3. 发明申请

US20070079219A1 SEMICONDUCTOR MEMORY DEVICE HAVING DATA HOLDING MODE USING ECC FUNCTION 失效
标题翻译：具有使用ECC功能的数据保存模式的半导体存储器件
公开(公告)号：US20070079219A1
公开(公告)日：2007-04-05
申请号：US11531895
申请日：2006-09-14
申请人： Takeshi Nagai , Shinji Miyano
发明人： Takeshi Nagai , Shinji Miyano
IPC分类号： G11C29/00
CPC分类号： G06F11/106 , G11C2029/0411
摘要： When memory cells enter an operation mode which performs only data holding, a control circuit controls the memory cells and an ECC circuit as follows. A plurality of data are read out to generate and store a check bit for error detection and correction. Refreshing is performed in a period within the error occurrence allowable range of an error correcting operation performed by the ECC circuit by using the check bit. Before a normal operation mode is restored from the operation mode which performs only data holding, an error bit of the data is corrected by using the check bit. In an entry/exit period, read/write and an ECC operation are sequentially performed for all the memory cells by a page mode operation. Memory cells connected to a word line which is not accessed by the page mode operation are sequentially activated and refreshed.
摘要翻译：当存储单元进入仅执行数据保持的操作模式时，控制电路如下控制存储单元和ECC电路。读取多个数据以生成并存储用于错误检测和校正的校验位。通过使用校验位，在由ECC电路执行的纠错操作的误差发生允许范围内的时间段内进行刷新。在仅执行数据保持的操作模式恢复正常操作模式之前，通过使用校验位来校正数据的错误位。在入口/出口期间，通过页面模式操作对所有存储器单元顺序执行读/写和ECC操作。连接到不被页模式操作访问的字线的存储单元被依次激活和刷新。

4. 发明申请

US20060221729A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060221729A1
公开(公告)日：2006-10-05
申请号：US11194539
申请日：2005-08-02
申请人： Hitoshi Iwai , Shinji Miyano
发明人： Hitoshi Iwai , Shinji Miyano
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0405 , G11C2029/1208 , G11C2229/743 , G11C2229/746 , G11C2229/763 , G11C2229/766
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a plurality of redundancy sections respectively provided for the plurality of memory blocks and configured to be substituted for defective memory cells, a test circuit that carries out a test on the memory cell array and outputs defective data, first and second memory circuit that temporarily store the defective data, a first write circuit that writes the defective data alternately in the first and second memory circuits, a first read circuit that reads the defective data alternately from the first and second memory circuits, a plurality of third memory circuits respectively provided for the plurality of memory blocks, that store the defective data, and a second write circuit that writes defective data read by the first read circuit in a third memory circuit corresponding to a memory block in which an error occurred.
摘要翻译：一种半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，多个冗余部分，分别为多个存储器块提供并被配置为代替有缺陷的存储器单元;测试电路，对存储器进行测试单元阵列并输出缺陷数据，临时存储缺陷数据的第一和第二存储器电路，将缺陷数据交替地写入第一和第二存储器电路的第一写入电路，从第一个存储器电路交替读取缺陷数据的第一读取电路和第二存储器电路，分别为存储有缺陷数据的多个存储器块提供的多个第三存储器电路;以及第二写入电路，其将由第一读取电路读取的缺陷数据写入与存储器相对应的第三存储器电路中阻塞发生错误。

5. 发明授权

US06154406A Dynamic random access memory capable of simultaneously writing identical data to memory cells 有权
标题翻译：动态随机存取存储器能够同时将相同的数据写入存储单元
公开(公告)号：US06154406A
公开(公告)日：2000-11-28
申请号：US320553
申请日：1999-05-27
申请人： Shinji Miyano , Toshimasa Namekawa , Masaharu Wada
发明人： Shinji Miyano , Toshimasa Namekawa , Masaharu Wada
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4087 , G11C11/4096 , G11C11/4097 , G11C7/1006 , G11C2207/104 , G11C2207/229
摘要： Where a first bit line pair comprises a first bit line and a second bit line, a first memory cell is located at an intersection between a selected word line and the first bit line. Where a second bit line pair comprises a third bit line and a fourth bit line, a second memory cell is located at an intersection between the selected word line and the fourth bit line. A data line pair comprises a first data line and a second data line. A first column switch comprises a first transistor connected between the first bit line and the first data line and a second transistor connected between the second bit line and the second data line. A second column switch comprises a third transistor connected between the third bit line and the first data line and a fourth transistor connected between the fourth bit line and the second data line. A column decoder turns on one of the first column switch and the second column switch in a normal-write mode, and turns on both the first column switch and the second column switch in a block-write mode. In the block-write mode, a potential of the first bit line and a potential of the fourth bit line are complementary to each other. Identical data is written to the first memory cell and the second memory cell.
摘要翻译：在第一位线对包括第一位线和第二位线的情况下，第一存储器单元位于所选字线和第一位线之间的交叉点处。在第二位线对包括第三位线和第四位线的情况下，第二存储器单元位于所选字线和第四位线之间的交叉点处。数据线对包括第一数据线和第二数据线。第一列开关包括连接在第一位线和第一数据线之间的第一晶体管和连接在第二位线和第二数据线之间的第二晶体管。第二列开关包括连接在第三位线和第一数据线之间的第三晶体管和连接在第四位线和第二数据线之间的第四晶体管。列解码器以正常写入模式打开第一列开关和第二列开关中的一个，并以块写模式打开第一列开关和第二列开关。在块写入模式中，第一位线的电位和第四位线的电位彼此互补。将相同的数据写入第一存储单元和第二存储单元。

6. 发明授权

US6002631A Semiconductor memory device having a mode in which a plurality of data are simultaneously read out of memory cells of one row and different columns 失效
标题翻译：具有从一行和不同列的存储单元中同时读出多个数据的模式的半导体存储器件
公开(公告)号：US6002631A
公开(公告)日：1999-12-14
申请号：US982534
申请日：1997-12-02
申请人： Ryo Haga , Tomoaki Yabe , Shinji Miyano
发明人： Ryo Haga , Tomoaki Yabe , Shinji Miyano
IPC分类号： G11C11/409 , G11C7/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C7/1018 , G11C7/1045 , G11C8/12
摘要： Even-numbered columns are arranged in the first memory cell array (bank), and odd-numbered columns are arranged in the second memory cell array (bank). A column address signal is input to an adder through a buffer. When data is read out of two or more columns, the adder generates a column address signal whose address value is more than that of the column address signal by one. The adder supplies a first column decoder with a column address signal for addressing an even-numbered column and supplies a second column decoder with a column address signal for addressing an odd-numbered column. Since the even-numbered columns and odd-numbered columns are arranged in their separate memory cell arrays, data read out of continuous two or more columns do not collide with each other.
摘要翻译：偶数列布置在第一存储单元阵列（bank）中，奇数列排列在第二存储单元阵列（bank）中。列地址信号通过缓冲器输入到加法器。当从两个或多个列读出数据时，加法器产生地址值大于列地址信号的列地址信号。加法器为第一列解码器提供列地址信号，用于寻址偶数列，并向第二列解码器提供用于寻址奇数列的列地址信号。由于偶数列和奇数列排列在其分开的存储单元阵列中，所以从连续的两个或更多个列读出的数据不会彼此冲突。

7. 发明申请

US20060200728A1 Synchronous semiconductor storage device having error correction function 失效
标题翻译：具有纠错功能的同步半导体存储装置
公开(公告)号：US20060200728A1
公开(公告)日：2006-09-07
申请号：US11274402
申请日：2005-11-16
申请人： Takeshi Nagai , Shinji Miyano
发明人： Takeshi Nagai , Shinji Miyano
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C7/1039 , G11C7/1072 , G11C11/4093 , G11C11/4096 , G11C2029/0411 , G11C2207/104
摘要： A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines. The write operation allows the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines. Further, in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.
摘要翻译：半导体存储器件具有其中布置多个存储器单元并与时钟信号同步操作的存储单元阵列。在同一周期的时钟信号中执行读写操作。读操作允许由第一列地址指定的读列选择线将读数据总线连接到位线。写操作允许由第二列地址指定的写列选择线将写数据总线连接到位线。此外，在写入操作中，通过将由校正子产生电路和校正电路进行了纠错的数据与输入到输入电路的数据组合而获得的数据由代码生成电路编码并写入记忆细胞

8. 发明授权

US06906384B2 Semiconductor device having one of patterned SOI and SON structure 失效
标题翻译：具有图案化SOI和SON结构之一的半导体器件
公开(公告)号：US06906384B2
公开(公告)日：2005-06-14
申请号：US10096655
申请日：2002-03-14
申请人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
发明人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
IPC分类号： H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/10861 , H01L21/76243 , H01L21/823481 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/1203 , H01L29/78639
摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.
摘要翻译：半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。第一半导体层设置在半导体衬底上并与之电连接。第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

9. 发明授权

US06529399B1 Semiconductor device realized by using partial SOI technology 失效
公开(公告)号：US06529399B1
公开(公告)日：2003-03-04
申请号：US10115977
申请日：2002-04-05
申请人： Toshimasa Namekawa , Shinji Miyano , Atsushi Suzuki
发明人： Toshimasa Namekawa , Shinji Miyano , Atsushi Suzuki
IPC分类号： G11C1124
CPC分类号： H01L27/10897 , H01L27/0218
摘要： A semiconductor substrate has a bulk region and a semiconductor region formed either on a buried insulating film or on a cavity region. The bulk region contains a plurality of memory cells, sense amplifiers and column selection gates, while the semiconductor region contains word line selection circuits and column selection circuits.

10. 发明授权

US5930187A One-chip LSI including a general memory and a logic 失效
标题翻译：单片LSI包括一般存储器和逻辑
公开(公告)号：US5930187A
公开(公告)日：1999-07-27
申请号：US962358
申请日：1997-10-31
申请人： Katsuhiko Sato , Shinji Miyano
发明人： Katsuhiko Sato , Shinji Miyano
IPC分类号： G06F15/78 , G01R31/3185 , G11C5/02 , G11C11/401 , G11C29/12 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/12 , G01R31/318538 , G11C5/025 , Y10S257/909
摘要： An LSI chip has a main surface occupied by a logic section, a data input/output section and a memory macro section. The memory macro section is a rectangular section arranged on the main surface of the LSI chip. A test control circuit is arranged along one side of the memory macro section. A data input/output circuit is arranged along another side of the memory macro section. The test control circuit may be arranged along one side of the LSI chip. Test data is supplied from the test control circuit to the data input/output circuit through a data bus. As a result, a load of designing a memory logic LSI can be lightened.
摘要翻译： LSI芯片具有由逻辑部分占据的主表面，数据输入/输出部分和存储宏部分。存储器宏部分是布置在LSI芯片的主表面上的矩形部分。测试控制电路沿着存储宏部分的一侧布置。数据输入/输出电路沿着存储器宏部分的另一侧布置。测试控制电路可以沿着LSI芯片的一侧布置。测试数据通过数据总线从测试控制电路提供给数据输入/输出电路。结果，可以减轻设计存储器逻辑LSI的负担。

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