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1. 发明授权

US08203882B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08203882B2
公开(公告)日：2012-06-19
申请号：US12718353
申请日：2010-03-05
申请人： Tomoo Hishida , Yoshihisa Iwata
发明人： Tomoo Hishida , Yoshihisa Iwata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.
摘要翻译：当在一个存储单元块中执行数据擦除操作时，将第一电压施加到从一个存储单元块中的m个源极线中选择的一个源极线。在数据擦除操作开始之前等于源极线的电压的第二电压被施加到其它源极线。然后，在施加第一电压的一定的时间延迟之后，将小于第一电压的第三电压施加到连接到所选择的源极线的源极侧选择晶体管的第三导电层。然后，由于第一和第三电压之间的电位差，在第三栅极绝缘层附近产生空穴电流。将第四电压施加到连接到要擦除的存储晶体管之一的第一导电层之一。其他第一导电层进入浮置状态。

2. 发明申请

US20130248975A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20130248975A1
公开(公告)日：2013-09-26
申请号：US13607702
申请日：2012-09-08
申请人： Tomoo HISHIDA , Yoshihisa Iwata
发明人： Tomoo HISHIDA , Yoshihisa Iwata
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/76849 , H01L21/76885 , H01L23/53266 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile semiconductor memory device includes a peripheral circuit having multilayer wirings. Above this peripheral circuit, a plurality of memory strings is formed. The memory strings include a plurality of memory cells and a back gate transistor connected in series. Multiple back gate layers are formed to function as a control electrode of the back gate transistor. A first connection part composed of semiconductor films connects a lower surface of one of the back gate layers and an upper surface of the uppermost wiring layer of the multilayer wirings, and a barrier metal film is disposed above the uppermost wiring layer.
摘要翻译：非易失性半导体存储器件包括具有多层布线的外围电路。在该外围电路上方形成多个存储器串。存储器串包括串联连接的多个存储单元和背栅晶体管。多个背栅层被形成为用作背栅晶体管的控制电极。由半导体膜构成的第一连接部分将背栅层之一的下表面和多层布线的最上布线层的上表面连接，并且阻挡金属膜设置在最上布线层的上方。

3. 发明申请

US20130003433A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130003433A1
公开(公告)日：2013-01-03
申请号：US13423546
申请日：2012-03-19
申请人： Tomoo HISHIDA , Yoshihisa IWATA
发明人： Tomoo HISHIDA , Yoshihisa IWATA
IPC分类号： G11C5/02
CPC分类号： H01L27/11582 , G11C5/025 , G11C5/04 , G11C5/063 , G11C7/18 , G11C8/12 , G11C16/0483 , G11C2213/71 , H01L23/528 , H01L27/10 , H01L27/11568 , H01L27/11575 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

4. 发明授权

US08315097B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08315097B2
公开(公告)日：2012-11-20
申请号：US13026616
申请日：2011-02-14
申请人： Tomoo Hishida , Hitoshi Iwai , Yoshihisa Iwata
发明人： Tomoo Hishida , Hitoshi Iwai , Yoshihisa Iwata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , H01L27/11582
摘要： A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.
摘要翻译：存储器串由多个存储晶体管和备用存储晶体管串联连接。字线连接到存储晶体管的栅极。备用字线连接到备用存储晶体管的栅极。存储器串包括第一半导体层，电荷存储层，多个第一导电层和第二导电层。第一半导体层相对于基板在垂直方向上延伸。电荷存储层包围第一半导体层的侧表面。多个第一导电层围绕第一半导体层的侧表面，电荷存储层位于其间，并用作字线。第二导电层围绕第一半导体层的侧表面，电荷存储层位于其间，用作备用字线。

5. 发明申请

US20120069655A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120069655A1
公开(公告)日：2012-03-22
申请号：US13026616
申请日：2011-02-14
申请人： Tomoo Hishida , Hitoshi Iwai , Yoshihisa Iwata
发明人： Tomoo Hishida , Hitoshi Iwai , Yoshihisa Iwata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/11582
摘要： A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.
摘要翻译：存储器串由多个存储晶体管和备用存储晶体管串联连接。字线连接到存储晶体管的栅极。备用字线连接到备用存储晶体管的栅极。存储器串包括第一半导体层，电荷存储层，多个第一导电层和第二导电层。第一半导体层相对于基板在垂直方向上延伸。电荷存储层包围第一半导体层的侧表面。多个第一导电层围绕第一半导体层的侧表面，电荷存储层位于其间，并用作字线。第二导电层围绕第一半导体层的侧表面，电荷存储层位于其间，用作备用字线。

6. 发明申请

US20110013454A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110013454A1
公开(公告)日：2011-01-20
申请号：US12726858
申请日：2010-03-18
申请人： Tomoo Hishida , Yoshihisa Iwata , Megumi Ishiduki , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhel Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoo Hishida , Yoshihisa Iwata , Megumi Ishiduki , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhel Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C5/025 , G11C5/02 , G11C5/04 , G11C16/0483 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.
摘要翻译：非易失性半导体存储器件包括：多个第一存储器串; 第一选择晶体管，其一端连接到第一存储器串的一端; 通常连接到多个第一选择晶体管的另一端的第一线; 开关电路，其一端连接到第一线; 以及通常连接到多个开关电路的另一端的第二线。开关电路控制第二线和第一线之间的电连接。

7. 发明申请

US20100238732A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20100238732A1
公开(公告)日：2010-09-23
申请号：US12718353
申请日：2010-03-05
申请人： Tomoo HISHIDA , Yoshihisa Iwata
发明人： Tomoo HISHIDA , Yoshihisa Iwata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.
摘要翻译：当在一个存储单元块中执行数据擦除操作时，将第一电压施加到从一个存储单元块中的m个源极线中选择的一个源极线。在数据擦除操作开始之前等于源极线的电压的第二电压被施加到其它源极线。然后，在施加第一电压的一定的时间延迟之后，将小于第一电压的第三电压施加到连接到所选择的源极线的源极侧选择晶体管的第三导电层。然后，由于第一和第三电压之间的电位差，在第三栅极绝缘层附近产生空穴电流。将第四电压施加到连接到要擦除的存储晶体管之一的第一导电层之一。其他第一导电层进入浮置状态。

8. 发明授权

US08861279B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08861279B2
公开(公告)日：2014-10-14
申请号：US13605840
申请日：2012-09-06
申请人： Tomoo Hishida , Yoshihisa Iwata
发明人： Tomoo Hishida , Yoshihisa Iwata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/30 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： A semiconductor storage device has a nonvolatile storage region, a voltage generating circuit that generates an operational voltage for the storage region, and a control circuit that sends the voltage generated by the voltage generating circuit to the storage region. The voltage generating circuit has a transistor, a first resistance element, a second resistance element, and a comparator. The first resistance element and the second resistance element have wiring structure for resistance. The resistance wiring in the wiring structure has the same line width as the finest line width in the wiring formed in the storage region.
摘要翻译：半导体存储装置具有非易失性存储区域，产生用于存储区域的工作电压的电压产生电路以及将由电压产生电路产生的电压发送到存储区域的控制电路。电压产生电路具有晶体管，第一电阻元件，第二电阻元件和比较器。第一电阻元件和第二电阻元件具有用于电阻的布线结构。布线结构中的电阻布线具有与形成在存储区域中的布线中的最细线宽度相同的线宽。

9. 发明授权

US08797777B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08797777B2
公开(公告)日：2014-08-05
申请号：US13423546
申请日：2012-03-19
申请人： Tomoo Hishida , Yoshihisa Iwata
发明人： Tomoo Hishida , Yoshihisa Iwata
IPC分类号： G11C5/02
CPC分类号： H01L27/11582 , G11C5/025 , G11C5/04 , G11C5/063 , G11C7/18 , G11C8/12 , G11C16/0483 , G11C2213/71 , H01L23/528 , H01L27/10 , H01L27/11568 , H01L27/11575 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
摘要翻译：半导体存储器件包括：半导体衬底; 多个存储单元，设置在所述半导体衬底上，并且每个存储单元包括堆叠的多个存储单元; 以及多个位线形成在沿列方向排列的多个存储器单元中的每一个上，多个位线的行方向上的对准间距小于存储单元的行方向上的对准间距，并且在列方向上排列的每个存储单元的一端连接到形成在沿列方向排列的多个存储单元上的多个位线之一。

10. 发明申请

US20100214838A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20100214838A1
公开(公告)日：2010-08-26
申请号：US12694690
申请日：2010-01-27
申请人： TOMOO HISHIDA , YOSHIHISA IWATA , KIYOTARO ITAGAKI , TAKASHI MAEDA
发明人： TOMOO HISHIDA , YOSHIHISA IWATA , KIYOTARO ITAGAKI , TAKASHI MAEDA
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3454 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer.
摘要翻译：非挥发性半导体存储装置包括执行擦除操作以从存储晶体管中选定的一个擦除数据的控制电路。控制电路向所选择的一个选择晶体管的另一端施加第一电压，使所选择的一个选择晶体管导通，并且使存储晶体管中的任何一个导通比接近选择晶体管更接近选择晶体管选择一个存储晶体管。控制电路还将低于第一电压的第二电压施加到所选存储晶体管的栅极。第一电压和第二电压之间的这种电位差导致电荷存储层中的电荷变化。

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