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1. 发明授权

US5050127A Memory device with improved common data line bias arrangement 失效
标题翻译：具有改进的公共数据线偏置布置的存储器件
公开(公告)号：US5050127A
公开(公告)日：1991-09-17
申请号：US423947
申请日：1989-10-19
申请人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
发明人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
IPC分类号： G11C11/417 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051
摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

2. 发明授权

US4829479A Memory device with improved common data line bias arrangement 失效
标题翻译：具有改进的公共数据线偏置布置的存储器件
公开(公告)号：US4829479A
公开(公告)日：1989-05-09
申请号：US108623
申请日：1987-10-15
申请人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
发明人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
IPC分类号： G11C11/417 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051
摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.
摘要翻译：一种存储器件，其中使用多个阻抗元件分压由最高工作电压下降固定电压的电压，并且公共数据线被分压电压偏置。由于施加了来自最高工作电位的固定电压降低的电压，即使当阻抗元件的电阻值降低时，流过阻抗元件路径的电流也不会显着增加，并且获得低功耗。由于阻抗元件的电阻值降低，所以由寄生于公共数据线的电阻和杂散电容确定的时间常数减小。因此，与存储在存储单元中的信息对应地产生的公用数据线的电位变化加快，数据检测时间缩短，可以缩短访问时间。

3. 发明授权

US4748487A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4748487A
公开(公告)日：1988-05-31
申请号：US053479
申请日：1987-05-26
申请人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
发明人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
IPC分类号： H01L21/8238 , G11C11/34 , G11C11/419 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/02
CPC分类号： G11C11/419 , H01L27/11
摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
摘要翻译：一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。维持上拉MISFET（Qp，Qp）和在互补数据线D和上拉和下降D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，两个MISFET的形成是相同的形状。此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

4. 发明授权

US4682200A Semiconductor memory device with matched equivalent series resistances to the complementary data lines 失效
标题翻译：半导体存储器件与互补数据线具有匹配的等效串联电阻
公开(公告)号：US4682200A
公开(公告)日：1987-07-21
申请号：US851485
申请日：1986-04-14
申请人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
发明人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
IPC分类号： H01L21/8238 , G11C11/34 , G11C11/419 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/02
CPC分类号： G11C11/419 , H01L27/11
摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.P) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
摘要翻译：一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。维持上拉MISFET（＆upbar＆Qp，＆upbar＆QP）和互补数据线D，＆upbar和D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，形成了两个MISFET 具有相同的形状。此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

5. 发明授权

US4665505A Write circuit for use in semiconductor storage device 失效
标题翻译：用于半导体存储设备的写电路
公开(公告)号：US4665505A
公开(公告)日：1987-05-12
申请号：US685552
申请日：1984-12-24
申请人： Nobuaki Miyakawa , Yoshiaki Yazawa , Shoichi Ozeki , Kinya Mitsumoto
发明人： Nobuaki Miyakawa , Yoshiaki Yazawa , Shoichi Ozeki , Kinya Mitsumoto
IPC分类号： G11C11/413 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1096 , G11C7/1078
摘要： A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.
摘要翻译：一种用于半导体存储装置的写入电路，包括由包括至少一个MOS晶体管逻辑电路和双极晶体管的复合电路构成的数据输出级。 Mos晶体管电路响应于输入信号而工作，以控制至少一个双极晶体管的导通截止状态。写入电路实现更少的功耗。

6. 发明授权

US4578693A Semiconductive photodetector device 失效
标题翻译：半导体光电探测器
公开(公告)号：US4578693A
公开(公告)日：1986-03-25
申请号：US505447
申请日：1983-06-17
申请人： Yoshiaki Yazawa , Nobuaki Miyakawa , Toji Mukai , Takahide Ikeda , Tatsuya Kamei
发明人： Yoshiaki Yazawa , Nobuaki Miyakawa , Toji Mukai , Takahide Ikeda , Tatsuya Kamei
IPC分类号： H01L27/146 , H01L31/0216 , H01L31/10 , H01L27/14 , H01L31/00
CPC分类号： H01L27/14643 , H01L31/02164
摘要： In a semiconductive photodetector device having a semiconductor substrate and a plurality of photodiodes juxtaposed in one major surface of the semiconductor substrate, exposed edges of adjacent pn junctions of adjacent photodiodes are covered with a polysilicon film.
摘要翻译：在具有半导体衬底和并置在半导体衬底的一个主表面上的多个光电二极管的半导体光电检测器件中，相邻光电二极管的相邻pn结的暴露边缘被多晶硅膜覆盖。

7. 发明授权

US07355270B2 Semiconductor chip with coil antenna and communication system 有权
标题翻译：半导体芯片采用线圈天线和通讯系统
公开(公告)号：US07355270B2
公开(公告)日：2008-04-08
申请号：US11030058
申请日：2005-01-07
申请人： Takehiko Hasebe , Yasushi Goto , Kouichi Uesaka , Yoshiaki Yazawa , Makoto Torigoe
发明人： Takehiko Hasebe , Yasushi Goto , Kouichi Uesaka , Yoshiaki Yazawa , Makoto Torigoe
IPC分类号： H01L23/02
CPC分类号： H01Q1/2225 , G06K7/10178 , G06K19/07749 , G06K19/07756 , G06K19/07775 , G06K19/07779 , G06K19/07783 , G06K19/07784 , H01L23/48 , H01L23/5227 , H01L2223/6677 , H01L2224/04105 , H01L2924/0002 , H01L2924/3011 , H01Q1/22 , H01Q7/00 , H01L2924/00
摘要： The present invention intends to prevent the communication distance from becoming shorter with a reduction in size of a coil antenna to the chip size and with a consequent decrease of an induced voltage. According to the present invention there is provided a semiconductor chip having a coil antenna and a circuit surface and adapted to transmit and receive signals by radio to and from an external device. The semiconductor chip has a configuration for increasing an electromagnetic coupling coefficient between the coil antenna and the external device. According to a concrete example thereof, a magnetic material is disposed, the coil antenna is formed by a stacked structure comprising plural conductor layers and insulating layers superimposed one on another, or the coil antenna is disposed outside an external form of a circuit of the semiconductor chip.
摘要翻译：本发明旨在通过将线圈天线的尺寸减小到芯片尺寸以及由此导致的感应电压降低来防止通信距离变短。根据本发明，提供一种具有线圈天线和电路表面的半导体芯片，其适于通过无线电向外部设备发送和接收信号。半导体芯片具有用于增加线圈天线和外部设备之间的电磁耦合系数的配置。根据其具体实例，设置磁性材料，线圈天线由包括多个导体层和彼此重叠的绝缘层的堆叠结构形成，或者线圈天线设置在半导体的电路的外部形式的外部芯片。

8. 发明申请

US20070176772A1 RFID tag, RFID reader/writer, RFID system, and processing method of RFID system 有权
标题翻译： RFID标签，RFID读写器，RFID系统和RFID系统的处理方法
公开(公告)号：US20070176772A1
公开(公告)日：2007-08-02
申请号：US11491990
申请日：2006-07-25
申请人： Ryo Nemoto , Hiroshi Yoshigi , Yoshiaki Yazawa , Kazuki Watanabe
发明人： Ryo Nemoto , Hiroshi Yoshigi , Yoshiaki Yazawa , Kazuki Watanabe
IPC分类号： G08B1/08 , H04Q5/22 , G08B13/14
CPC分类号： G06K19/0717 , G06K7/0008 , G06K19/0701 , G06K19/0723
摘要： In an RFID system including RFID tags each incorporating a sensor, accuracy of measurement by the sensor can be improved. For example, when measurements are performed several times by using RFID tags each incorporating a sensor unit, generation of a carrier directed from an RFID reader/writer to the RFID tags is stopped for a predetermined period every time when a measurement ends. By this means, the chip temperature of the RFID tag increased due to power consumption in each measurement can be reduced to, for example, ambient temperature every time when a measurement ends. Therefore, an error in measurement by the sensor unit can be reduced, thereby achieving accurate measurement.
摘要翻译：在包括RFID传感器的RFID标签中，传感器的测量精度可以提高。例如，当通过使用包含传感器单元的RFID标签进行多次测量时，每当测量结束时，停止从RFID读取器/写入器引导到RFID标签的载体的预定时间的生成。通过这种方式，每次测量结束时，每个测量中的功率消耗增加的RFID标签的芯片温度可以降低到例如环境温度。因此，可以降低传感器单元的测量误差，从而实现精确的测量。

9. 发明申请

US20060066451A1 Transponder and a sensing system using the transponder 有权
标题翻译：应答器和使用转发器的传感系统
公开(公告)号：US20060066451A1
公开(公告)日：2006-03-30
申请号：US11036011
申请日：2005-01-18
申请人： Ryo Nemoto , Tadashi Oonishi , Kazuki Watanabe , Yoshiaki Yazawa , Yasushi Goto , Hiroshi Yoshigi
发明人： Ryo Nemoto , Tadashi Oonishi , Kazuki Watanabe , Yoshiaki Yazawa , Yasushi Goto , Hiroshi Yoshigi
IPC分类号： G08B1/08 , G08B13/14 , G08C19/16
CPC分类号： G06K19/0717 , G06K19/0723
摘要： A measuring system enabled to simultaneously start measurement by a plurality of transponders by communication between a reader/writer and a plurality of transponders each with a built-in sensor is to be provided. In addition to an identifier SID intrinsic to a sensor and a chip identifier TID intrinsic to a transponder chip, a unique identifier UID combining the sensor SID and the chip TID is provided in each transponder. A reader/writer, in designating a transponder and transmitting a measurement command to it, invalidates the chip TID out of the UID of each transponder, validates only information regarding a sensor function, and transmits measurement commands including action commands unique to each type of sensor.
摘要翻译：提供一种能够通过读取器/写入器和多个具有内置传感器的转发器之间的通信由多个转发器同时开始测量的测量系统。除了传感器固有的标识符SID和应答器芯片固有的芯片标识符TID之外，在每个应答器中提供组合传感器SID和芯片TID的唯一标识符UID。读写器在指定应答器并向其发送测量命令时，使每个应答器的UID中的芯片TID无效，仅验证关于传感器功能的信息，并且发送包括每种类型的传感器唯一的动作命令的测量命令。

10. 发明授权

US5028867A Printed-wiring board 失效
标题翻译：印刷电路板
公开(公告)号：US5028867A
公开(公告)日：1991-07-02
申请号：US401302
申请日：1989-08-31
申请人： Yoshiaki Yazawa
发明人： Yoshiaki Yazawa
IPC分类号： G01B7/31 , G01R31/28 , H05K1/02 , H05K3/00 , H05K3/12
CPC分类号： G01R31/2818 , G01B7/31 , H05K1/0269 , H05K2201/09781 , H05K2203/163 , H05K2203/166 , H05K3/0052 , H05K3/0097 , H05K3/1216
摘要： In a printed-wiring board produced by arranging a plurality of wiring circuit patterns on a printed-wiring board by screen printing and cutting out product regions corresponding to the wiring circuit patterns by punching them along the circumferences of the product regions, the printed-wiring board according to the present invention comprises deviation detecting patterns for determining whether or not the condition of deviation of the printed pattern is within an allowable limit, the deviation detecting patterns being printed at the time of the screen printing of the wiring circuit patterns in the vicinity of the position of the cut plane of the board for each product region of each wiring circuit pattern. Thereby, it is made possible to easily determine whether or not the condition of the pattern deviation is within a specified allowable limit.
摘要翻译：在通过丝网印刷在印刷电路板上布置多个布线电路图案并通过沿着产品区域的周边冲压而切除与布线电路图案相对应的产品区域而制造的印刷布线板中，印刷布线根据本发明的板包括用于确定打印图案的偏离条件是否在可允许极限内的偏差检测图案，在布线电路图案的丝网印刷附近打印的偏差检测图案在附近对于每个布线电路图案的每个产品区域的板的切割平面的位置。由此，能够容易地判断图案偏差的条件是否在规定的允许极限内。

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