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1. 发明授权

US5050127A Memory device with improved common data line bias arrangement 失效
标题翻译：具有改进的公共数据线偏置布置的存储器件
公开(公告)号：US5050127A
公开(公告)日：1991-09-17
申请号：US423947
申请日：1989-10-19
申请人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
发明人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
IPC分类号： G11C11/417 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051
摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

2. 发明授权

US4829479A Memory device with improved common data line bias arrangement 失效
标题翻译：具有改进的公共数据线偏置布置的存储器件
公开(公告)号：US4829479A
公开(公告)日：1989-05-09
申请号：US108623
申请日：1987-10-15
申请人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
发明人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
IPC分类号： G11C11/417 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051
摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.
摘要翻译：一种存储器件，其中使用多个阻抗元件分压由最高工作电压下降固定电压的电压，并且公共数据线被分压电压偏置。由于施加了来自最高工作电位的固定电压降低的电压，即使当阻抗元件的电阻值降低时，流过阻抗元件路径的电流也不会显着增加，并且获得低功耗。由于阻抗元件的电阻值降低，所以由寄生于公共数据线的电阻和杂散电容确定的时间常数减小。因此，与存储在存储单元中的信息对应地产生的公用数据线的电位变化加快，数据检测时间缩短，可以缩短访问时间。

3. 发明授权

US4748487A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4748487A
公开(公告)日：1988-05-31
申请号：US053479
申请日：1987-05-26
申请人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
发明人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
IPC分类号： H01L21/8238 , G11C11/34 , G11C11/419 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/02
CPC分类号： G11C11/419 , H01L27/11
摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
摘要翻译：一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。维持上拉MISFET（Qp，Qp）和在互补数据线D和上拉和下降D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，两个MISFET的形成是相同的形状。此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

4. 发明授权

US4682200A Semiconductor memory device with matched equivalent series resistances to the complementary data lines 失效
标题翻译：半导体存储器件与互补数据线具有匹配的等效串联电阻
公开(公告)号：US4682200A
公开(公告)日：1987-07-21
申请号：US851485
申请日：1986-04-14
申请人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
发明人： Hideaki Uchida , Kinya Mitsumoto , Yoshiaki Yazawa , Shinji Nakazato , Masanori Odaka
IPC分类号： H01L21/8238 , G11C11/34 , G11C11/419 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/02
CPC分类号： G11C11/419 , H01L27/11
摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.P) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.
摘要翻译：一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。维持上拉MISFET（＆upbar＆Qp，＆upbar＆QP）和互补数据线D，＆upbar和D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，形成了两个MISFET 具有相同的形状。此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

5. 发明授权

US4858189A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4858189A
公开(公告)日：1989-08-15
申请号：US121914
申请日：1987-11-17
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
摘要翻译：为了提供高速度和低功耗，构造半导体集成电路以利用CMOS元件和双极晶体管。双极晶体管用于输出部分以利用其运行速度，以允许输出线的快速充电和放电。同时，电路的主要工作部分使用低功耗的CMOS元件。这种布置在存储器电路中是特别有利的。

6. 发明授权

US4713796A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4713796A
公开(公告)日：1987-12-15
申请号：US701226
申请日：1985-02-13
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
摘要翻译：为了提供高速度和低功耗，构造半导体集成电路以利用CMOS元件和双极晶体管。双极晶体管用于输出部分以利用其运行速度，以允许输出线的快速充电和放电。同时，电路的主要工作部分使用低功耗的CMOS元件。这种布置在存储器电路中是特别有利的。

7. 发明授权

US5311482A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5311482A
公开(公告)日：1994-05-10
申请号：US93511
申请日：1993-07-16
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
摘要翻译：为了提供高速度和低功耗，构造半导体集成电路以利用CMOS元件和双极晶体管。双极晶体管用于输出部分以利用其运行速度，以允许输出线的快速充电和放电。同时，电路的主要工作部分使用低功耗的CMOS元件。这种布置在存储器电路中是特别有利的。

8. 发明授权

US5371713A Semiconductor integrated circuit 失效
公开(公告)号：US5371713A
公开(公告)日：1994-12-06
申请号：US207677
申请日：1994-03-09
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

9. 发明授权

US5042010A Semiconductor integrated circuit 失效
公开(公告)号：US5042010A
公开(公告)日：1991-08-20
申请号：US520620
申请日：1990-05-08
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and lower power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portiosn of the circuit use CMOS elements of lower power consumption. This arrangement is particulary advantageous in memory circuits.

10. 发明授权

US4924439A Semiconductor integrated circuit 失效
公开(公告)号：US4924439A
公开(公告)日：1990-05-08
申请号：US358262
申请日：1989-05-30
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

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