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    • 3. 发明授权
    • Wiring structure of liquid crystal display panel having gate, source and drain electrodes horizontally staggered
    • 具有栅极,源极和漏极的液晶显示面板的布线结构水平交错
    • US08520179B2
    • 2013-08-27
    • US12630568
    • 2009-12-03
    • Liang-Hao KangYi-Cheng Tsai
    • Liang-Hao KangYi-Cheng Tsai
    • G02F1/1343G02F1/1345
    • G02F1/13452G02F1/136286G02F2001/136295
    • A wiring structure of a liquid crystal display (LCD) panel is provided. The wiring structure includes: a gate electrode layer, formed on a glass substrate; a first insulating layer, covering the glass substrate and partially formed on the gate electrode layer, such that at least one first opening is defined on the gate electrode layer; a source/drain electrode layer, formed on the first insulating layer, in which the source/drain electrode layer and the gate electrode layer are horizontally staggered; a second insulating layer, partially formed on the source/drain electrode layer, and defining at least one second opening on the source/drain electrode layer; and an indium tin oxide (ITO) layer, formed on the first opening, the second opening, and/or the second insulating layer. Thus, the high impedance of the ITO layer for connecting the gate electrode layer with the source/drain electrode layer is reduced.
    • 提供了液晶显示(LCD)面板的布线结构。 布线结构包括:形成在玻璃基板上的栅电极层; 第一绝缘层,覆盖玻璃基板并部分地形成在栅极电极层上,使得至少一个第一开口限定在栅极电极层上; 源极/漏极电极层,形成在第一绝缘层上,其中源极/漏极电极层和栅极电极层水平交错; 第二绝缘层,部分地形成在源极/漏极电极层上,并且在源极/漏极电极层上限定至少一个第二开口; 和形成在第一开口,第二开口和/或第二绝缘层上的氧化铟锡(ITO)层。 因此,用于连接栅极电极层与源极/漏极电极层的ITO层的高阻抗减小。
    • 5. 发明授权
    • Transistor array substrate
    • 晶体管阵列基板
    • US08232554B2
    • 2012-07-31
    • US13043112
    • 2011-03-08
    • Dian-Gan LiaoYi-Cheng Tsai
    • Dian-Gan LiaoYi-Cheng Tsai
    • H01L29/04
    • G02F1/133351G02F2001/136254H01L27/124
    • A transistor array substrate includes a substrate, plural pads, plural shorting bars, at least one pixel array, plural first wires, and plural second wires. The substrate has at least one panel region and a peripheral circuit region surrounding the panel region. The pads and the shorting bars are disposed in the peripheral circuit region. The pixel array, the first wires, and the second wires are disposed in the panel region. The panel region has a pair of first edges and a pair of second edges. The first edges are connected between the second edges. The shorting bars are connected to the pads. The first wires and the second wires are electrically connected to the pixel array. The first wires are connected to some shorting bars through one of the first edges. The second wires are connected to the other shorting bars through at least one second edge.
    • 晶体管阵列基板包括基板,多个焊盘,多个短路棒,至少一个像素阵列,多个第一布线和多个第二布线。 衬底具有至少一个面板区域和围绕面板区域的外围电路区域。 焊盘和短路棒设置在外围电路区域中。 像素阵列,第一线和第二线设置在面板区域中。 面板区域具有一对第一边缘和一对第二边缘。 第一边缘连接在第二边缘之间。 短路棒连接到焊盘。 第一线和第二线电连接到像素阵列。 第一导线通过第一边缘之一连接到一些短路棒。 第二导线通过至少一个第二边缘连接到另一个短路棒。