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1. 发明授权

US08018423B2 Shift register and liquid crystal display 有权
标题翻译：移位寄存器和液晶显示
公开(公告)号：US08018423B2
公开(公告)日：2011-09-13
申请号：US12108546
申请日：2008-04-24
申请人： Yi-Cheng Tsai , Chien-Ting Chan , Hsi-Rong Han , Wen-Chun Wang , Kuo-Chang Su
发明人： Yi-Cheng Tsai , Chien-Ting Chan , Hsi-Rong Han , Wen-Chun Wang , Kuo-Chang Su
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G09G2330/021 , G11C19/28
摘要： A shift register is for generating scan signals. Each stage of the shift register comprises a first level lifting unit and at least a second level lifting unit, a first level lowering unit and at least a second level lowering unit, first and second driving units. The first level lowering and lifting units are for controlling the levels of signals at the first output terminal to output a first scan signal. The second level lowering unit and second level lifting unit are for controlling the levels of signals at the second output terminal to output at least a second scan signal. The first and second driving units are for turning on and off the first and the second level lifting units and the first and the second level lowering unit to control the first and second scan signals.
摘要翻译：移位寄存器用于产生扫描信号。移位寄存器的每个级包括第一级提升单元和至少第二级提升单元，第一级降级单元和至少第二级降级单元，第一和第二驱动单元。第一级降低和提升单元用于控制第一输出端子处的信号电平以输出第一扫描信号。第二电平降低单元和第二电平提升单元用于控制第二输出端子处的信号电平以输出至少第二扫描信号。第一和第二驱动单元用于打开和关闭第一和第二电平提升单元以及第一和第二电平降低单元以控制第一和第二扫描信号。

2. 发明申请

US20080266275A1 SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY 有权
标题翻译： SHIFT寄存器和液晶显示器
公开(公告)号：US20080266275A1
公开(公告)日：2008-10-30
申请号：US12108546
申请日：2008-04-24
申请人： Yi-Cheng Tsai , Chien-Ting Chan , Hsi-Rong Han , Wen-Chun Wang , Kuo-Chang Su
发明人： Yi-Cheng Tsai , Chien-Ting Chan , Hsi-Rong Han , Wen-Chun Wang , Kuo-Chang Su
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G09G2330/021 , G11C19/28
摘要： A shift register is for generating scan signals. Each stage of the shift register comprises a first level lifting unit and at least a second level lifting unit, a first level lowering unit and at least a second level lowering unit, first and second driving units. The first level lowering and lifting units are for controlling the levels of signals at the first output terminal to output a first scan signal. The second level lowering unit and second level lifting unit are for controlling the levels of signals at the second output terminal to output at least a second scan signal. The first and second driving units are for turning on and off the first and the second level lifting units and the first and the second level lowering unit to control the first and second scan signals.
摘要翻译：移位寄存器用于产生扫描信号。移位寄存器的每个级包括第一级提升单元和至少第二级提升单元，第一级降级单元和至少第二级降级单元，第一和第二驱动单元。第一级降低和提升单元用于控制第一输出端子处的信号电平以输出第一扫描信号。第二电平降低单元和第二电平提升单元用于控制第二输出端子处的信号电平以输出至少第二扫描信号。第一和第二驱动单元用于打开和关闭第一和第二电平提升单元以及第一和第二电平降低单元以控制第一和第二扫描信号。

3. 发明申请

US20120206434A1 Shift Register 审中-公开
标题翻译：移位寄存器
公开(公告)号：US20120206434A1
公开(公告)日：2012-08-16
申请号：US13454952
申请日：2012-04-24
申请人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
发明人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.
摘要翻译：移位寄存器包括许多级，并且每个级包括第一级，第二级和第三级控制单元以及第一和第二控制单元。第一和第二电平控制单元分别向输出端提供第一时钟信号和电压。第一驱动单元和电平控制单元耦合到第一节点。响应于下一级的输入信号，第二控制信号和第一控制信号，第一驱动单元接通并关断第一电平控制单元。第二驱动单元响应于第一控制信号而导通和关闭第二电平控制单元。第三电平控制单元响应于第二控制信号和第一控制信号向输出端提供第一电压。

4. 发明申请

US20080016139A1 Shift register with each stage controlled by a specific voltage of the next stage and the stage after thereof 有权
标题翻译：每个级的移位寄存器由下一级的特定电压和其后的级控制
公开(公告)号：US20080016139A1
公开(公告)日：2008-01-17
申请号：US11822899
申请日：2007-07-11
申请人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
发明人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
IPC分类号： G06F7/44
CPC分类号： G11C19/28 , G09G3/3674
摘要： A shift register has shift register units. The nth shift register unit includes first to third level control units and first and second driving units. The first and second level control units respectively provide a first clock signal and a first voltage to an output terminal. The first driving unit and the first level control unit are coupled to a first node, and a voltage on the first node is a first control signal. The first driving unit turns on and off the first level control unit in response to an input signal and second and third control signals. The second driving unit turns on and off the second level control unit in response to the first control signal. The third level control unit provides the first voltage to the output terminal in response to a front edge of the first control signal of the (n+2)th shift register unit.
摘要翻译：移位寄存器具有移位寄存器单元。第n级移位寄存器单元包括第一至第三电平控制单元和第一和第二驱动单元。第一和第二电平控制单元分别向输出端提供第一时钟信号和第一电压。第一驱动单元和第一电平控制单元耦合到第一节点，并且第一节点上的电压是第一控制信号。第一驱动单元响应于输入信号和第二和第三控制信号而打开和关闭第一电平控制单元。第二驱动单元响应于第一控制信号而打开和关闭第二电平控制单元。第三电平控制单元响应于第（n + 2）个第（＆）移位寄存器单元的第一控制信号的前沿向输出端提供第一电压。

5. 发明申请

US20100245300A1 Shift Register 有权
标题翻译：移位寄存器
公开(公告)号：US20100245300A1
公开(公告)日：2010-09-30
申请号：US12727287
申请日：2010-03-19
申请人： Chien-Ting Chan , Wen-Chun Wang , Hsi-Rong Han , Kuo-Chang Su
发明人： Chien-Ting Chan , Wen-Chun Wang , Hsi-Rong Han , Kuo-Chang Su
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/0286
摘要： A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m−1)th stage output signal provided by an (m−1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.
摘要翻译：提供了包括多个多级移位寄存器电路的移位寄存器。第m级移位寄存器电路包括一个节点，一个移位寄存器单元和一个控制电路。节点上定义了第m个周期启用的第一个控制信号。移位寄存器单元由第（m-1）级移位寄存器电路提供的第（m-1）级输出信号和用于在第m个周期中提供使能的第m级输出信号的时钟信号控制，并由由第（m + 1）级移位寄存器电路提供的第（m + 1）级第二控制信号，用于在第（m + 1）个周期中提供不能使用的第m级输出信号。由时钟信号控制的控制电路根据第m级第一控制信号向第（m-1）级移位寄存器电路提供第m级第二控制信号，其中m是大于1的自然数。

6. 发明授权

US08055695B2 Shift register with each stage controlled by a specific voltage of the next stage and the stage after thereof 有权
标题翻译：每个级的移位寄存器由下一级的特定电压和其后的级控制
公开(公告)号：US08055695B2
公开(公告)日：2011-11-08
申请号：US11822899
申请日：2007-07-11
申请人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
发明人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
IPC分类号： G06F7/00 , G06F15/00 , G09G3/36
CPC分类号： G11C19/28 , G09G3/3674
摘要： A shift register has shift register units. The nth shift register unit includes first to third level control units and first and second driving units. The first and second level control units respectively provide a first clock signal and a first voltage to an output terminal. The first driving unit and the first level control unit are coupled to a first node, and a voltage on the first node is a first control signal. The first driving unit turns on and off the first level control unit in response to an input signal and second and third control signals. The second driving unit turns on and off the second level control unit in response to the first control signal. The third level control unit provides the first voltage to the output terminal in response to a front edge of the first control signal of the (n+2)th shift register unit.
摘要翻译：移位寄存器具有移位寄存器单元。第n移位寄存器单元包括第一至第三电平控制单元和第一和第二驱动单元。第一和第二电平控制单元分别向输出端提供第一时钟信号和第一电压。第一驱动单元和第一电平控制单元耦合到第一节点，并且第一节点上的电压是第一控制信号。第一驱动单元响应于输入信号和第二和第三控制信号而打开和关闭第一电平控制单元。第二驱动单元响应于第一控制信号而打开和关闭第二电平控制单元。第三电平控制单元响应于第（n + 2）移位寄存器单元的第一控制信号的前沿向输出端提供第一电压。

7. 发明授权

US08970467B2 Shift register and gate driver with compensation control 有权
标题翻译：移位寄存器和栅极驱动器，具有补偿控制
公开(公告)号：US08970467B2
公开(公告)日：2015-03-03
申请号：US12727287
申请日：2010-03-19
申请人： Chien-Ting Chan , Wen-Chun Wang , Hsi-Rong Han , Kuo-Chang Su
发明人： Chien-Ting Chan , Wen-Chun Wang , Hsi-Rong Han , Kuo-Chang Su
IPC分类号： G09G3/36 , G11C19/28
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/0286
摘要： A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m−1)th stage output signal provided by an (m−1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.
摘要翻译：提供了包括多个多级移位寄存器电路的移位寄存器。第m级移位寄存器电路包括一个节点，一个移位寄存器单元和一个控制电路。节点上定义了第m个周期启用的第一个控制信号。移位寄存器单元由第（m-1）级移位寄存器电路提供的第（m-1）级输出信号和用于在第m个周期中提供使能的第m级输出信号的时钟信号控制，并由由第（m + 1）级移位寄存器电路提供的第（m + 1）级第二控制信号，用于在第（m + 1）个周期中提供不能使用的第m级输出信号。由时钟信号控制的控制电路根据第m级第一控制信号向第（m-1）级移位寄存器电路提供第m级第二控制信号，其中m是大于1的自然数。

8. 发明授权

US08208598B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08208598B2
公开(公告)日：2012-06-26
申请号：US12275455
申请日：2008-11-21
申请人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
发明人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
IPC分类号： G11C19/00
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.
摘要翻译：移位寄存器包括许多级，并且每个级包括第一级，第二级和第三级控制单元以及第一和第二控制单元。第一和第二电平控制单元分别向输出端提供第一时钟信号和电压。第一驱动单元和电平控制单元耦合到第一节点。响应于下一级的输入信号，第二控制信号和第一控制信号，第一驱动单元接通并关断第一电平控制单元。第二驱动单元响应于第一控制信号而导通和关闭第二电平控制单元。第三电平控制单元响应于第二控制信号和第一控制信号向输出端提供第一电压。

9. 发明申请

US20090128541A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20090128541A1
公开(公告)日：2009-05-21
申请号：US12275455
申请日：2008-11-21
申请人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
发明人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.
摘要翻译：移位寄存器包括许多级，并且每个级包括第一级，第二级和第三级控制单元以及第一和第二控制单元。第一和第二电平控制单元分别向输出端提供第一时钟信号和电压。第一驱动单元和电平控制单元耦合到第一节点。响应于下一级的输入信号，第二控制信号和第一控制信号，第一驱动单元接通并关断第一电平控制单元。第二驱动单元响应于第一控制信号而导通和关闭第二电平控制单元。第三电平控制单元响应于第二控制信号和第一控制信号向输出端提供第一电压。

10. 发明申请

US20080001899A1 FLAT DISPLAY STRUCTURE 审中-公开
标题翻译：平面显示结构
公开(公告)号：US20080001899A1
公开(公告)日：2008-01-03
申请号：US11608933
申请日：2006-12-11
申请人： Chien-Ting Chan , Yi-Cheng Tsai , Hsi-Rong Han , Wen-Tui Liao
发明人： Chien-Ting Chan , Yi-Cheng Tsai , Hsi-Rong Han , Wen-Tui Liao
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286
摘要： A flat display structure includes a substrate, a pixel array, a first-stage shift register and a second-stage shift register. The substrate includes a signal line. The pixel array is disposed on the substrate. The first-stage shift register is disposed at a first side of the pixel array and coupled to the signal line for outputting a first-stage scan signal to the pixel array according to trigger of a first start pulse. The second-stage shift register is disposed at a second side of the pixel array and coupled to the signal line for receiving a second start pulse via the signal line.
摘要翻译：平面显示结构包括基板，像素阵列，第一级移位寄存器和第二级移位寄存器。衬底包括信号线。像素阵列设置在基板上。第一级移位寄存器设置在像素阵列的第一侧并且耦合到信号线，用于根据第一起始脉冲的触发将第一级扫描信号输出到像素阵列。第二级移位寄存器设置在像素阵列的第二侧并且耦合到信号线，用于经由信号线接收第二起始脉冲。

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