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1. 发明授权

US08520179B2 Wiring structure of liquid crystal display panel having gate, source and drain electrodes horizontally staggered 有权
标题翻译：具有栅极，源极和漏极的液晶显示面板的布线结构水平交错
公开(公告)号：US08520179B2
公开(公告)日：2013-08-27
申请号：US12630568
申请日：2009-12-03
申请人： Liang-Hao Kang , Yi-Cheng Tsai
发明人： Liang-Hao Kang , Yi-Cheng Tsai
IPC分类号： G02F1/1343 , G02F1/1345
CPC分类号： G02F1/13452 , G02F1/136286 , G02F2001/136295
摘要： A wiring structure of a liquid crystal display (LCD) panel is provided. The wiring structure includes: a gate electrode layer, formed on a glass substrate; a first insulating layer, covering the glass substrate and partially formed on the gate electrode layer, such that at least one first opening is defined on the gate electrode layer; a source/drain electrode layer, formed on the first insulating layer, in which the source/drain electrode layer and the gate electrode layer are horizontally staggered; a second insulating layer, partially formed on the source/drain electrode layer, and defining at least one second opening on the source/drain electrode layer; and an indium tin oxide (ITO) layer, formed on the first opening, the second opening, and/or the second insulating layer. Thus, the high impedance of the ITO layer for connecting the gate electrode layer with the source/drain electrode layer is reduced.
摘要翻译：提供了液晶显示（LCD）面板的布线结构。布线结构包括：形成在玻璃基板上的栅电极层; 第一绝缘层，覆盖玻璃基板并部分地形成在栅极电极层上，使得至少一个第一开口限定在栅极电极层上; 源极/漏极电极层，形成在第一绝缘层上，其中源极/漏极电极层和栅极电极层水平交错; 第二绝缘层，部分地形成在源极/漏极电极层上，并且在源极/漏极电极层上限定至少一个第二开口; 和形成在第一开口，第二开口和/或第二绝缘层上的氧化铟锡（ITO）层。因此，用于连接栅极电极层与源极/漏极电极层的ITO层的高阻抗减小。

2. 发明授权

US08390651B2 Driving method and driving apparatus for displaying apparatus 有权
标题翻译：用于显示装置的驱动方法和驱动装置
公开(公告)号：US08390651B2
公开(公告)日：2013-03-05
申请号：US12430881
申请日：2009-04-27
申请人： Kuei-Wei Huang , Yi-Cheng Tsai , Qi-Ming Lu , Jhen-Shen Liao , Kuan-Hung Liu
发明人： Kuei-Wei Huang , Yi-Cheng Tsai , Qi-Ming Lu , Jhen-Shen Liao , Kuan-Hung Liu
IPC分类号： G09G5/10
CPC分类号： G09G3/3648 , G09G3/36 , G09G2340/16
摘要： A driving method for driving a display apparatus is provided. The driving method includes: configuring a plurality of driving voltages corresponding to a plurality of gray scales, where the gray scales include a first gray scale and a second gray scale smaller than the first gray scale, and a first driving voltage corresponding to the first gray scale is lower than a second driving voltage corresponding to the second gray scale; and controlling the display apparatus to display a gray scale merely up to the second gray scale. In this way, the driving method hence reduces the response time of the display apparatus, which may be an LCD display panel.
摘要翻译：提供一种用于驱动显示装置的驱动方法。驱动方法包括：配置与多个灰度级相对应的多个驱动电压，其中所述灰度级包括小于所述第一灰度级的第一灰度级和第二灰度级，以及对应于所述第一灰度级的第一驱动电压规模低于对应于第二灰度级的第二驱动电压; 并且控制显示装置仅显示直到第二灰阶的灰度。以这种方式，驱动方法因此减少了可以是LCD显示面板的显示装置的响应时间。

3. 发明授权

US08232554B2 Transistor array substrate 有权
标题翻译：晶体管阵列基板
公开(公告)号：US08232554B2
公开(公告)日：2012-07-31
申请号：US13043112
申请日：2011-03-08
申请人： Dian-Gan Liao , Yi-Cheng Tsai
发明人： Dian-Gan Liao , Yi-Cheng Tsai
IPC分类号： H01L29/04
CPC分类号： G02F1/133351 , G02F2001/136254 , H01L27/124
摘要： A transistor array substrate includes a substrate, plural pads, plural shorting bars, at least one pixel array, plural first wires, and plural second wires. The substrate has at least one panel region and a peripheral circuit region surrounding the panel region. The pads and the shorting bars are disposed in the peripheral circuit region. The pixel array, the first wires, and the second wires are disposed in the panel region. The panel region has a pair of first edges and a pair of second edges. The first edges are connected between the second edges. The shorting bars are connected to the pads. The first wires and the second wires are electrically connected to the pixel array. The first wires are connected to some shorting bars through one of the first edges. The second wires are connected to the other shorting bars through at least one second edge.
摘要翻译：晶体管阵列基板包括基板，多个焊盘，多个短路棒，至少一个像素阵列，多个第一布线和多个第二布线。衬底具有至少一个面板区域和围绕面板区域的外围电路区域。焊盘和短路棒设置在外围电路区域中。像素阵列，第一线和第二线设置在面板区域中。面板区域具有一对第一边缘和一对第二边缘。第一边缘连接在第二边缘之间。短路棒连接到焊盘。第一线和第二线电连接到像素阵列。第一导线通过第一边缘之一连接到一些短路棒。第二导线通过至少一个第二边缘连接到另一个短路棒。

4. 发明申请

US20100141293A1 LCD PANELS CAPABLE OF DETECTING CELL DEFECTS, LINE DEFECTS AND LAYOUT DEFECTS 审中-公开
标题翻译：检测细胞缺陷的液晶面板，线路缺陷和布局缺陷
公开(公告)号：US20100141293A1
公开(公告)日：2010-06-10
申请号：US12357412
申请日：2009-01-22
申请人： Ying-Hui Chen , Yi-Cheng Tsai
发明人： Ying-Hui Chen , Yi-Cheng Tsai
IPC分类号： G01R31/00
CPC分类号： G09G3/006 , G09G3/3648
摘要： An LCD panel includes a plurality of signal lines, a plurality of display units, a driving circuit and a test unit. Each display unit is coupled to a corresponding signal line of the plurality of signal lines. The driving circuit is coupled to corresponding signals lines via a plurality of output ends. The test unit includes a shorting bar, a test pad, and a plurality of switches. Each switch is coupled between a corresponding signal line of the plurality of signal lines and the shorting bar.
摘要翻译： LCD面板包括多条信号线，多个显示单元，驱动电路和测试单元。每个显示单元耦合到多个信号线的相应信号线。驱动电路经由多个输出端耦合到对应的信号线。测试单元包括短路棒，测试垫和多个开关。每个开关耦合在多个信号线的相应信号线和短路棒之间。

5. 发明申请

US20080266275A1 SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY 有权
标题翻译： SHIFT寄存器和液晶显示器
公开(公告)号：US20080266275A1
公开(公告)日：2008-10-30
申请号：US12108546
申请日：2008-04-24
申请人： Yi-Cheng Tsai , Chien-Ting Chan , Hsi-Rong Han , Wen-Chun Wang , Kuo-Chang Su
发明人： Yi-Cheng Tsai , Chien-Ting Chan , Hsi-Rong Han , Wen-Chun Wang , Kuo-Chang Su
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G09G2330/021 , G11C19/28
摘要： A shift register is for generating scan signals. Each stage of the shift register comprises a first level lifting unit and at least a second level lifting unit, a first level lowering unit and at least a second level lowering unit, first and second driving units. The first level lowering and lifting units are for controlling the levels of signals at the first output terminal to output a first scan signal. The second level lowering unit and second level lifting unit are for controlling the levels of signals at the second output terminal to output at least a second scan signal. The first and second driving units are for turning on and off the first and the second level lifting units and the first and the second level lowering unit to control the first and second scan signals.
摘要翻译：移位寄存器用于产生扫描信号。移位寄存器的每个级包括第一级提升单元和至少第二级提升单元，第一级降级单元和至少第二级降级单元，第一和第二驱动单元。第一级降低和提升单元用于控制第一输出端子处的信号电平以输出第一扫描信号。第二电平降低单元和第二电平提升单元用于控制第二输出端子处的信号电平以输出至少第二扫描信号。第一和第二驱动单元用于打开和关闭第一和第二电平提升单元以及第一和第二电平降低单元以控制第一和第二扫描信号。

6. 发明授权

US08921946B2 Integrated circuit resistor 有权
标题翻译：集成电路电阻
公开(公告)号：US08921946B2
公开(公告)日：2014-12-30
申请号：US13294251
申请日：2011-11-11
申请人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
发明人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
IPC分类号： H01L29/772 , H01L21/265 , H01L27/06 , H01L29/8605 , H01L29/66
CPC分类号： H01L28/20 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/26506 , H01L21/26513 , H01L21/823437 , H01L27/0629 , H01L29/66545 , H01L29/8605
摘要： A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
摘要翻译：半导体器件包括包括隔离区域的衬底和设置在隔离区域上的电阻器，其中电阻器包括具有反向盒状掺杂物分布的植入物，其使得电阻变化与随后的平坦化变化最小化。触点设置在电阻上。还提供了一种制造这种半导体器件的方法。

7. 发明授权

US08208598B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08208598B2
公开(公告)日：2012-06-26
申请号：US12275455
申请日：2008-11-21
申请人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
发明人： Yi-Cheng Tsai , Wen-Chun Wang , Hsi-Rong Han , Chien-Ting Chan
IPC分类号： G11C19/00
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.
摘要翻译：移位寄存器包括许多级，并且每个级包括第一级，第二级和第三级控制单元以及第一和第二控制单元。第一和第二电平控制单元分别向输出端提供第一时钟信号和电压。第一驱动单元和电平控制单元耦合到第一节点。响应于下一级的输入信号，第二控制信号和第一控制信号，第一驱动单元接通并关断第一电平控制单元。第二驱动单元响应于第一控制信号而导通和关闭第二电平控制单元。第三电平控制单元响应于第二控制信号和第一控制信号向输出端提供第一电压。

8. 发明申请

US20120104419A1 TRANSISTOR ARRAY SUBSTRATE 有权
标题翻译：晶体管阵列基板
公开(公告)号：US20120104419A1
公开(公告)日：2012-05-03
申请号：US13043112
申请日：2011-03-08
申请人： Dian-Gan LIAO , Yi-Cheng Tsai
发明人： Dian-Gan LIAO , Yi-Cheng Tsai
IPC分类号： H01L27/15
CPC分类号： G02F1/133351 , G02F2001/136254 , H01L27/124
摘要： A transistor array substrate includes a substrate, plural pads, plural shorting bars, at least one pixel array, plural first wires, and plural second wires. The substrate has at least one panel region and a peripheral circuit region surrounding the panel region. The pads and the shorting bars are disposed in the peripheral circuit region. The pixel array, the first wires, and the second wires are disposed in the panel region. The panel region has a pair of first edges and a pair of second edges. The first edges are connected between the second edges. The shorting bars are connected to the pads. The first wires and the second wires are electrically connected to the pixel array. The first wires are connected to some shorting bars through one of the first edges. The second wires are connected to the other shorting bars through at least one second edge
摘要翻译：晶体管阵列基板包括基板，多个焊盘，多个短路棒，至少一个像素阵列，多个第一布线和多个第二布线。衬底具有至少一个面板区域和围绕面板区域的外围电路区域。焊盘和短路棒设置在外围电路区域中。像素阵列，第一线和第二线设置在面板区域中。面板区域具有一对第一边缘和一对第二边缘。第一边缘连接在第二边缘之间。短路棒连接到焊盘。第一线和第二线电连接到像素阵列。第一导线通过第一边缘之一连接到一些短路棒。第二导线通过至少一个第二边缘连接到另一个短路棒

9. 发明申请

US20120092321A1 LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：液晶显示器
公开(公告)号：US20120092321A1
公开(公告)日：2012-04-19
申请号：US13029104
申请日：2011-02-16
申请人： YEN-FEN LIN , Yi-cheng Tsai
发明人： YEN-FEN LIN , Yi-cheng Tsai
IPC分类号： G09G3/36 , G06F3/038
CPC分类号： G02F1/136286 , G02F1/136213 , G02F2201/40 , G09G3/3648 , G09G2300/0465
摘要： An LCD includes a first pixel electrode coupled to a first scan line and a data line, and a second pixel electrode coupled to a second scan line and the data line. A first and a second storage capacitor electrode lines are at two sides of the data line and across the scan lines. A first storage capacitor electrode extension line is extended out of the first storage capacitor electrode line and toward the data line, and a second storage capacitor electrode extension line is extended out of the second storage capacitor electrode line and toward the data line. The first pixel electrode and second pixel electrode partly overlap the first and the second storage capacitor electrode extension lines, respectively. Since the storage capacitor electrode line and the scan line is formed on different metal layer, a gap between the storage capacitor electrode line and the scan line is shortened.
摘要翻译： LCD包括耦合到第一扫描线和数据线的第一像素电极，以及耦合到第二扫描线和数据线的第二像素电极。第一和第二存储电容器电极线位于数据线的两侧并跨越扫描线。第一存储电容电极延长线从第一辅助电容电极线延伸出并朝向数据线，第二辅助电容电极延长线从第二辅助电容电极线延伸出并朝向数据线。第一像素电极和第二像素电极分别与第一和第二存储电容器电极延长线重叠。由于存储电容电极线和扫描线形成在不同的金属层上，所以存储电容电极线与扫描线之间的间隙缩短。

10. 发明授权

US08018539B2 Pixel circuit structure 有权
标题翻译：像素电路结构
公开(公告)号：US08018539B2
公开(公告)日：2011-09-13
申请号：US12244906
申请日：2008-10-03
申请人： Yi-Cheng Tsai , I-Fang Wang , Wen-Chun Wang , Hen-Ta Kang , Kai-Lun Kuo , Ming-Chang Yu , Wan-Jen Tsai
发明人： Yi-Cheng Tsai , I-Fang Wang , Wen-Chun Wang , Hen-Ta Kang , Kai-Lun Kuo , Ming-Chang Yu , Wan-Jen Tsai
IPC分类号： G02F1/133
CPC分类号： G09G3/3648 , G09G3/3614 , G09G2300/0443 , G09G2300/0447 , G09G2300/0456 , G09G2320/028
摘要： A pixel circuit structure applied in an LCD panel, which has a common voltage and includes at least one data line, is provided. The pixel circuit structure includes a first and a second circuit. The first circuit includes a first switch and a first capacitor. The second circuit includes a second switch, a third switch and a second capacitor. One end of the first capacitor receives the common voltage. Two ends of the first switch are respectively coupled to the data line and the other end of the first capacitor. The second and the third switch are coupled serially between the data line and a voltage source. One end of the second capacitor receives the common voltage, and the other end is coupled between the second and the third switch. The potential difference between the two ends of the first capacitor is different from that of the second capacitor.
摘要翻译：提供了应用于具有公共电压并且包括至少一条数据线的LCD面板中的像素电路结构。像素电路结构包括第一和第二电路。第一电路包括第一开关和第一电容器。第二电路包括第二开关，第三开关和第二电容器。第一电容器的一端接收公共电压。第一开关的两端分别耦合到第一电容器的数据线和另一端。第二和第三开关串联连接在数据线和电压源之间。第二电容器的一端接收公共电压，另一端耦合在第二和第三开关之间。第一电容器的两端之间的电位差与第二电容器的电位差不同。

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