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1. 发明授权

US06734458B2 Test pattern for measuring contact resistance and method of manufacturing the same 失效
标题翻译：用于测量接触电阻的测试图案及其制造方法
公开(公告)号：US06734458B2
公开(公告)日：2004-05-11
申请号：US10029390
申请日：2001-12-28
申请人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
发明人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device. At this time, a first line contact region and a second line contact region are formed between a word line so that a line contact region can form a pair; a plurality of sources are formed in the first line contact region and a plurality of sources are formed in the second line contact region wherein neighboring sources are connected by diffusion layers so that the first line contact region and the second line contact region can be electrically connected; and a plurality of line contact patterns are formed so that the plurality of the sources can be electrically connected by every two in each of the first and second line contact regions wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned. Therefore, the present invention can allow current for measuring the resistance sequentially along the first line contact region and the second line contact region to measure the line contact resistance in which the contact resistance in every source portion is considered.
摘要翻译：本发明涉及一种测量接触电阻的测试图案及其制造方法。为了确认在进行用于制造该器件的实际工艺之前适用于半导体器件的接触电阻，本发明根据实际应用于实际的线路接触的设计规则来设计用于测量接触电阻的测试图案设备。此时，在字线之间形成第一线接触区域和第二线路接触区域，使得线路接触区域可以形成一对; 多个源极形成在第一线路接触区域中，并且多个源极形成在第二线路接触区域中，其中相邻源极通过扩散层连接，使得第一线路接触区域和第二线路接触区域可以电连接 ; 并且形成多个线接触图案，使得多个源可以在形成在第一线接触区域中的线接触图案和线接触图案的第一和第二线路接触区域中的每一个中每两个电连接一次形成在第二线接触区域中的交替位置。因此，本发明可以允许沿着第一线路接触区域和第二线路接触区域依次测量电阻的电流来测量考虑到每个源极部分中的接触电阻的线路接触电阻。

2. 发明授权

US06204125B1 Method of forming a gate in a stack gate flash EEPROM cell 有权
标题翻译：在堆叠栅极快速EEPROM单元中形成栅极的方法
公开(公告)号：US06204125B1
公开(公告)日：2001-03-20
申请号：US09605632
申请日：2000-06-28
申请人： Keun Woo Lee , Ki Seog Kim , Jin Shin , Sung Kee Park
发明人： Keun Woo Lee , Ki Seog Kim , Jin Shin , Sung Kee Park
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L21/28273
摘要： The present invention relates to a method of forming a gate in a stack gate flash EEPROM cell. In order to preventing a lateral bird's beak from occurring in an ONO dielectric layer during a reoxidation process to be performed after a formation of a cell gate having a stack structure formed by stacking a floating gate, an ONO dielectric layer and a control gate, an oxide layer and a nitride layer are sequentially formed on an entire structure before the reoxidation and after a formation of the cell gate. The oxide layer serves to reduce a stress in depositing the nitride layer, and the nitride layer serves to prevent an occurrence of the lateral bird's beak of the ONO dielectric layer during the reoxidation process. Accordingly, the present invention prevents the lateral bird's beak of the ONO dielectric layer, thereby improving a speed of cell erase operation.
摘要翻译：本发明涉及一种在堆叠栅极快闪EEPROM单元中形成栅极的方法。为了防止在形成具有通过堆叠浮栅，ONO电介质层和控制栅形成的堆叠结构的电池栅极的再氧化工艺期间在ONO电介质层中发生侧面鸟嘴，氧化层和氮化物层在再氧化之前和电池栅极形成之后的整个结构上依次形成。氧化物层用于减少沉积氮化物层的应力，并且氮化物层用于在再氧化过程期间防止ONO电介质层的侧面鸟喙的发生。因此，本发明能够防止ONO电介质层的横向鸟嘴，从而提高电池擦除操作的速度。

3. 发明授权

US07099198B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US07099198B2
公开(公告)日：2006-08-29
申请号：US10968687
申请日：2004-10-19
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.
摘要翻译：闪速存储器中的行解码器包括用于选择性地将字线耦合到第一电压端子的第一开关和用于选择性地将字线耦合到第二电压端子的第二开关。行解码器还包括用于选择性地将字线耦合到第三电压端子的第三开关。

4. 发明授权

US06819597B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US06819597B2
公开(公告)日：2004-11-16
申请号：US10614229
申请日：2003-07-07
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： Disclosed are a row decoder in a flash memory and erasing method in a flash memory cell using the same. The row decoder comprises a PMOS transistor having a gate electrode for receiving a first input signal as an input and connected between a first power supply terminal and a first node, a first NMOS transistor having a gate electrode for receiving the first input signal as an input and connected between the first node and a second node, a second NMOS transistor having a gate electrode for receiving the second input signal as an input and connected between the second node and a ground terminal, and a switching means having a gate electrode for receiving the third input signal as an input and connected between the second node and a second power supply terminal, wherein the first node is connected to word lines.
摘要翻译：本发明公开了一种闪速存储器中的行解码器和使用其的擦除方法。行解码器包括具有用于接收第一输入信号作为输入并连接在第一电源端子和第一节点之间的栅电极的PMOS晶体管，具有用于接收第一输入信号作为输入的栅电极的第一NMOS晶体管并连接在第一节点和第二节点之间的第二NMOS晶体管，具有用于接收第二输入信号作为输入并连接在第二节点和接地端子之间的栅电极的第二NMOS晶体管，以及具有栅电极的开关装置，第三输入信号作为输入并连接在第二节点和第二电源端子之间，其中第一节点连接到字线。

5. 发明授权

US06743676B2 Method of forming a floating gate in a flash memory device 失效
标题翻译：在闪速存储器件中形成浮动栅极的方法
公开(公告)号：US06743676B2
公开(公告)日：2004-06-01
申请号：US10286980
申请日：2002-11-04
申请人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
发明人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.
摘要翻译：本发明涉及一种在闪速存储器件中形成浮动栅极的方法。在形成器件隔离膜时，限定用于浮置栅极的下多晶硅层的空间，通过随后的良好牺牲氧化过程和阱氧化过程在沟槽的内表面上形成鸟嘴，以及上部多晶硅层形成浮栅，从而形成浮栅的空间。因此，与现有步进法相比，本发明可以降低成本，因为与自对准浮动模式相比，不需要使用化学机械抛光工艺（CMP）的平坦化处理，因此与现有的步进方法和工艺成本相比不需要掩模处理。

6. 发明授权

US06316313B1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US06316313B1
公开(公告)日：2001-11-13
申请号：US09717002
申请日：2000-11-22
申请人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
发明人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
IPC分类号： H01L218247
CPC分类号： H01L27/112
摘要： There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.
摘要翻译：公开了一种制造闪速存储器件的方法。为了解决现有的闪速存储器件的情况下阱电阻和寄生电容大的问题以及器件的擦除速度较慢的问题，本发明通过使用金属形成扇区单元的阱区硅化物层并且通过使用合金层来限定晶胞。因此，它可以降低阱电阻和寄生电容。此外，它可以提高装置的操作速度，并且可以通过允许单元单元的擦除操作来降低制造成本。

7. 发明授权

US07705395B2 Flash memory cell and method of manufacturing the same and programming/erasing reading method of flash memory cell 失效
标题翻译：闪存单元及其制造方法和闪存单元的编程/擦除读取方法
公开(公告)号：US07705395B2
公开(公告)日：2010-04-27
申请号：US12247305
申请日：2008-10-08
申请人： Sung Kee Park , Young Seon You , Yong Wook Kim , Yoo Nam Jeon
发明人： Sung Kee Park , Young Seon You , Yong Wook Kim , Yoo Nam Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115 , H01L29/7887
摘要： Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.
摘要翻译：公开了一种闪存单元及其制造方法及其编程/擦除/读取方法。闪速存储单元包括形成在半导体衬底的给定区域的第一隧道氧化物膜，形成在第一隧道氧化物膜上的第一浮栅，形成在半导体衬底上并沿着第一浮置区的一个侧壁的第二隧道氧化膜栅极，与第一沟槽氧化膜接触时与第一浮栅隔离的第二浮栅;形成在第一浮栅和第二浮栅上的电介质膜，形成在电介质膜上的控制栅，位于第二隧道氧化膜的一侧以下的半导体衬底，以及形成在第一隧道氧化膜的一侧以下的半导体衬底中的第二结区。因此，本发明可以使用现有的工艺技术来实现高密度的2比特单元或3比特单元。此外，鉴于电荷存储/保持以及编程时间，它可以降低制造成本并实现比传统闪存单元有利的高集成闪存单元。

8. 发明授权

US06884679B2 Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell 失效
标题翻译：闪存单元及其制造方法和闪存单元的编程/擦除/读取方法
公开(公告)号：US06884679B2
公开(公告)日：2005-04-26
申请号：US10616720
申请日：2003-07-10
申请人： Sung Kee Park , Young Seon You , Yong Wook Kim , Yoo Nam Jeon
发明人： Sung Kee Park , Young Seon You , Yong Wook Kim , Yoo Nam Jeon
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115 , H01L29/7887
摘要： Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.
摘要翻译：公开了一种闪存单元及其制造方法及其编程/擦除/读取方法。闪速存储单元包括形成在半导体衬底的给定区域的第一隧道氧化物膜，形成在第一隧道氧化物膜上的第一浮栅，形成在半导体衬底上并沿着第一浮置区的一个侧壁的第二隧道氧化膜栅极，与第一沟槽氧化膜接触时与第一浮栅隔离的第二浮栅;形成在第一浮栅和第二浮栅上的电介质膜，形成在电介质膜上的控制栅，位于第二隧道氧化膜的一侧以下的半导体衬底，以及形成在第一隧道氧化膜的一侧以下的半导体衬底中的第二结区。因此，本发明可以使用现有的工艺技术来实现高密度的2比特单元或3比特单元。此外，鉴于电荷存储/保持以及编程时间，它可以降低制造成本并实现比传统闪存单元有利的高集成闪存单元。

9. 发明授权

US08340397B2 Extensible system and method for stereo matching in real-time 有权
标题翻译：实时立体匹配的可扩展系统和方法
公开(公告)号：US08340397B2
公开(公告)日：2012-12-25
申请号：US11678428
申请日：2007-02-23
申请人： Jae Wook Jeon , Seung Hun Jin , Jung Uk Cho , Sung Kee Park , Munsang Kim , Kyoung Mu Lee , Jong Eun Byun
发明人： Jae Wook Jeon , Seung Hun Jin , Jung Uk Cho , Sung Kee Park , Munsang Kim , Kyoung Mu Lee , Jong Eun Byun
IPC分类号： G06K9/00 , G06K9/56 , G06K9/64 , G03B35/08
CPC分类号： G06K9/32 , G06T7/593 , G06T2207/10021
摘要： Disclosed are a system and a method extensible for performing, in real-time, stereo snatching for calculating depth images with a result of searching for points of similarity by using images taken with two cameras. The system includes a coordinate creating module, a census transform module, a delay XOR calculation module, a stereo matching module, and a control module. Accordingly, by using the system extensible for performing stereo matching, depth information of corrected images can be acquired in real-time without using computer systems or software programs for special purposes. Furthermore, since the system extensible for performing stereo matching can be simply realized by hardware, the system and the method of the present invention can be easily applied to actual intellectual-type robots, industrial settings, etc.
摘要翻译：公开了一种可扩展的系统和方法，用于实时地执行用于计算深度图像的立体声捕获，其结果是通过使用用两个相机拍摄的图像来搜索相似点。该系统包括坐标创建模块，普查变换模块，延迟XOR计算模块，立体匹配模块和控制模块。因此，通过使用可扩展的用于执行立体匹配的系统，可以实时获取校正图像的深度信息，而不用于特殊目的的计算机系统或软件程序。此外，由于用于执行立体匹配的可扩展的系统可以通过硬件简单地实现，所以本发明的系统和方法可以容易地应用于实际的智能机器人，工业设置等。

10. 发明授权

US08252661B2 Method of fabricating flash memory device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US08252661B2
公开(公告)日：2012-08-28
申请号：US12781777
申请日：2010-05-17
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , G11C16/0408 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth.
摘要翻译：半导体器件包括具有单元区域和周边区域的半导体衬底。单元阵列定义在单元区域内，单元阵列具有第一，第二，第三和第四面。第一解码器被限定在外围区域内并且被提供为与单元阵列的第一侧相邻。在设置在电池阵列的第一侧和周边区域之间的第一边界区域处形成第一隔离结构。第一有源区形成在设置在电池阵列的第二侧和周边区域之间的第二边界区域。第一隔离结构具有具有第一深度的第一部分和具有第二深度的第二部分。

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