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1. 发明授权

US06204125B1 Method of forming a gate in a stack gate flash EEPROM cell 有权
标题翻译：在堆叠栅极快速EEPROM单元中形成栅极的方法
公开(公告)号：US06204125B1
公开(公告)日：2001-03-20
申请号：US09605632
申请日：2000-06-28
申请人： Keun Woo Lee , Ki Seog Kim , Jin Shin , Sung Kee Park
发明人： Keun Woo Lee , Ki Seog Kim , Jin Shin , Sung Kee Park
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L21/28273
摘要： The present invention relates to a method of forming a gate in a stack gate flash EEPROM cell. In order to preventing a lateral bird's beak from occurring in an ONO dielectric layer during a reoxidation process to be performed after a formation of a cell gate having a stack structure formed by stacking a floating gate, an ONO dielectric layer and a control gate, an oxide layer and a nitride layer are sequentially formed on an entire structure before the reoxidation and after a formation of the cell gate. The oxide layer serves to reduce a stress in depositing the nitride layer, and the nitride layer serves to prevent an occurrence of the lateral bird's beak of the ONO dielectric layer during the reoxidation process. Accordingly, the present invention prevents the lateral bird's beak of the ONO dielectric layer, thereby improving a speed of cell erase operation.
摘要翻译：本发明涉及一种在堆叠栅极快闪EEPROM单元中形成栅极的方法。为了防止在形成具有通过堆叠浮栅，ONO电介质层和控制栅形成的堆叠结构的电池栅极的再氧化工艺期间在ONO电介质层中发生侧面鸟嘴，氧化层和氮化物层在再氧化之前和电池栅极形成之后的整个结构上依次形成。氧化物层用于减少沉积氮化物层的应力，并且氮化物层用于在再氧化过程期间防止ONO电介质层的侧面鸟喙的发生。因此，本发明能够防止ONO电介质层的横向鸟嘴，从而提高电池擦除操作的速度。

2. 发明授权

US06734458B2 Test pattern for measuring contact resistance and method of manufacturing the same 失效
标题翻译：用于测量接触电阻的测试图案及其制造方法
公开(公告)号：US06734458B2
公开(公告)日：2004-05-11
申请号：US10029390
申请日：2001-12-28
申请人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
发明人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device. At this time, a first line contact region and a second line contact region are formed between a word line so that a line contact region can form a pair; a plurality of sources are formed in the first line contact region and a plurality of sources are formed in the second line contact region wherein neighboring sources are connected by diffusion layers so that the first line contact region and the second line contact region can be electrically connected; and a plurality of line contact patterns are formed so that the plurality of the sources can be electrically connected by every two in each of the first and second line contact regions wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned. Therefore, the present invention can allow current for measuring the resistance sequentially along the first line contact region and the second line contact region to measure the line contact resistance in which the contact resistance in every source portion is considered.
摘要翻译：本发明涉及一种测量接触电阻的测试图案及其制造方法。为了确认在进行用于制造该器件的实际工艺之前适用于半导体器件的接触电阻，本发明根据实际应用于实际的线路接触的设计规则来设计用于测量接触电阻的测试图案设备。此时，在字线之间形成第一线接触区域和第二线路接触区域，使得线路接触区域可以形成一对; 多个源极形成在第一线路接触区域中，并且多个源极形成在第二线路接触区域中，其中相邻源极通过扩散层连接，使得第一线路接触区域和第二线路接触区域可以电连接 ; 并且形成多个线接触图案，使得多个源可以在形成在第一线接触区域中的线接触图案和线接触图案的第一和第二线路接触区域中的每一个中每两个电连接一次形成在第二线接触区域中的交替位置。因此，本发明可以允许沿着第一线路接触区域和第二线路接触区域依次测量电阻的电流来测量考虑到每个源极部分中的接触电阻的线路接触电阻。

3. 发明授权

US07099198B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US07099198B2
公开(公告)日：2006-08-29
申请号：US10968687
申请日：2004-10-19
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.
摘要翻译：闪速存储器中的行解码器包括用于选择性地将字线耦合到第一电压端子的第一开关和用于选择性地将字线耦合到第二电压端子的第二开关。行解码器还包括用于选择性地将字线耦合到第三电压端子的第三开关。

4. 发明授权

US06819597B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US06819597B2
公开(公告)日：2004-11-16
申请号：US10614229
申请日：2003-07-07
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： Disclosed are a row decoder in a flash memory and erasing method in a flash memory cell using the same. The row decoder comprises a PMOS transistor having a gate electrode for receiving a first input signal as an input and connected between a first power supply terminal and a first node, a first NMOS transistor having a gate electrode for receiving the first input signal as an input and connected between the first node and a second node, a second NMOS transistor having a gate electrode for receiving the second input signal as an input and connected between the second node and a ground terminal, and a switching means having a gate electrode for receiving the third input signal as an input and connected between the second node and a second power supply terminal, wherein the first node is connected to word lines.
摘要翻译：本发明公开了一种闪速存储器中的行解码器和使用其的擦除方法。行解码器包括具有用于接收第一输入信号作为输入并连接在第一电源端子和第一节点之间的栅电极的PMOS晶体管，具有用于接收第一输入信号作为输入的栅电极的第一NMOS晶体管并连接在第一节点和第二节点之间的第二NMOS晶体管，具有用于接收第二输入信号作为输入并连接在第二节点和接地端子之间的栅电极的第二NMOS晶体管，以及具有栅电极的开关装置，第三输入信号作为输入并连接在第二节点和第二电源端子之间，其中第一节点连接到字线。

5. 发明授权

US06743676B2 Method of forming a floating gate in a flash memory device 失效
标题翻译：在闪速存储器件中形成浮动栅极的方法
公开(公告)号：US06743676B2
公开(公告)日：2004-06-01
申请号：US10286980
申请日：2002-11-04
申请人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
发明人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.
摘要翻译：本发明涉及一种在闪速存储器件中形成浮动栅极的方法。在形成器件隔离膜时，限定用于浮置栅极的下多晶硅层的空间，通过随后的良好牺牲氧化过程和阱氧化过程在沟槽的内表面上形成鸟嘴，以及上部多晶硅层形成浮栅，从而形成浮栅的空间。因此，与现有步进法相比，本发明可以降低成本，因为与自对准浮动模式相比，不需要使用化学机械抛光工艺（CMP）的平坦化处理，因此与现有的步进方法和工艺成本相比不需要掩模处理。

6. 发明授权

US06316313B1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US06316313B1
公开(公告)日：2001-11-13
申请号：US09717002
申请日：2000-11-22
申请人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
发明人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
IPC分类号： H01L218247
CPC分类号： H01L27/112
摘要： There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.
摘要翻译：公开了一种制造闪速存储器件的方法。为了解决现有的闪速存储器件的情况下阱电阻和寄生电容大的问题以及器件的擦除速度较慢的问题，本发明通过使用金属形成扇区单元的阱区硅化物层并且通过使用合金层来限定晶胞。因此，它可以降低阱电阻和寄生电容。此外，它可以提高装置的操作速度，并且可以通过允许单元单元的擦除操作来降低制造成本。

7. 发明授权

US06391665B1 Method of monitoring a source contact in a flash memory 有权
标题翻译：监视闪存中的源触点的方法
公开(公告)号：US06391665B1
公开(公告)日：2002-05-21
申请号：US09722112
申请日：2000-11-27
申请人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
发明人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/04 , G11C29/50 , G11C29/50008 , G11C2029/5006 , H01L21/76895 , H01L27/115
摘要： There is disclosed a method of monitoring a source contact in a flash memory by which whether a source contact having a narrow contact area contacts or not can be easily monitored using over-erase cell characteristic in a flash cell, in a flash memory device in which a source line is formed by a local interconnection method. In the present invention, in order to monitor a contact state at source contacts, the same voltage to the erase condition of a cell is applied to respective terminals (VG terminal, VD terminal, VS terminal and VSS terminal) wherein all the electrons existing at a floating gate in all the cells connected to the VS terminal and VSS terminal become turned on so that they can be over-erased. On the other hands, as electrons existing at the floating gate in two cells shared by any source contacts having a defect contact are not erased, the cells remain turn-off. In this state, if test voltages (VG=0V, VD
摘要翻译：公开了一种监视闪速存储器中的源极触点的方法，通过该闪光存储器中的源极触点可以容易地利用闪存单元中的过擦除单元特性来容易地监视具有窄接触区域的源极触点的触点，源线由本地互连方式形成。在本发明中，为了监测源极触点的接触状态，将与电池的擦除状态相同的电压施加到各个端子（VG端子，VD端子，VS端子和VSS端子），其中所有电子存在于连接到VS端子和VSS端子的所有单元中的浮动栅极变为导通，使得它们可能被过擦除。另一方面，由于存在于由具有缺陷接触的任何源极触点共享的两个电池中的浮动栅极处的电子不被擦除，所以电池保持关断。在这种状态下，如果施加了测试电压（VG = 0V，VD <5V，VS =浮动，VSS =接地），则在具有接触缺陷的部分中，从VD端子到VSS端子的电流断开，从而允许要监控的源触点的接触状态。

8. 发明授权

US07848150B2 Flash memory device and method of operating the same 有权
标题翻译：闪存设备及其操作方法
公开(公告)号：US07848150B2
公开(公告)日：2010-12-07
申请号：US12055641
申请日：2008-03-26
申请人： Keun Woo Lee , Ki Seog Kim
发明人： Keun Woo Lee , Ki Seog Kim
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/349
摘要： A flash memory device and a method of operating the same is disclosed, in which the conditions of voltage (or current) applied during the reading operation are differently adjusted according to an accumulated number of times of a programming operation, an erasing operation or a reading operation (an accumulated number of operation cycle). Even if a level of the threshold voltage is changed to a level which differs from that of the target voltage by an increase of the accumulated number of operation cycle regardless of the programming operation (or the erasing operation) being normally performed, the reliability of the reading operation can be enhanced to prevent a malfunction of the memory cell from being generated.
摘要翻译：公开了一种闪速存储装置及其操作方法，其中根据编程操作，擦除操作或读取的累积次数，不同地调整在读取操作期间施加的电压（或电流）的条件操作（累计操作周期数）。即使通过正常执行编程操作（或擦除操作），通过累积操作周期数的增加，阈值电压的电平变化到与目标电压的电平不同的电平，则可靠性可以增强读取操作以防止生成存储器单元的故障。

9. 发明申请

US20100235105A1 METHOD FOR ANALYZING DYNAMIC DETECTABLE EVENTS AT THE SINGLE MOLECULE LEVEL 审中-公开
标题翻译：在单分子水平上分析动态检测事件的方法
公开(公告)号：US20100235105A1
公开(公告)日：2010-09-16
申请号：US12686372
申请日：2010-01-12
申请人： Andrei Volkov , Costa M. Colbert , Ivan Pan , Anelia Kraltcheva , Mitsu Reddy , Nasanshargal Battulga , Michael A. Rea , Keun Woo Lee , Susan H. Hardin , Brent Mulder , Chris Hebel , Alok Bandekar
发明人： Andrei Volkov , Costa M. Colbert , Ivan Pan , Anelia Kraltcheva , Mitsu Reddy , Nasanshargal Battulga , Michael A. Rea , Keun Woo Lee , Susan H. Hardin , Brent Mulder , Chris Hebel , Alok Bandekar
IPC分类号： G06F19/00
CPC分类号： C12Q1/6813 , G01N21/6408 , G01N21/6456 , G01N2021/6439
摘要： A method to be implemented on or in a computer is disclosed, where the method includes data collection, calibration, candidate selection, and analysis of data streams associated with each candidate to classify single molecule fluorescence resonance energy transfer events. Once classified, the classification can be related to the nature of the events, such as the identification of dNTP incorporation during primer extension to obtain a base read out of an unknown template.
摘要翻译：公开了一种在计算机上或计算机中实现的方法，其中该方法包括与每个候选物相关联的数据流的数据收集，校准，候选选择和分析，以分类单分子荧光共振能量传递事件。一旦分类，分类可以与事件的性质相关，例如在引物延伸期间鉴定dNTP并入以获得从未知模板读出的碱基。

10. 发明授权

US07095656B2 Method of erasing NAND flash memory device 失效
标题翻译：擦除NAND闪存器件的方法
公开(公告)号：US07095656B2
公开(公告)日：2006-08-22
申请号：US11007183
申请日：2004-12-09
申请人： Keun Woo Lee
发明人： Keun Woo Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Provided is concerned with a method of erasing a NAND flash memory device, capable of restraining an erasing disturbance fail arising from a deselected cell block and improving a product yield of the device by applying a negative voltage to a well of a high voltage transistor forming an X-decoder during an erasing operation in the NAND flash memory device.
摘要翻译：本发明涉及一种擦除NAND闪速存储器件的方法，该方法能够抑制由取消选择的单元块产生的擦除干扰故障，并通过向构成高压晶体管的高电压晶体管的阱施加负电压来提高器件的产品产量 NAND闪存器件中的擦除操作期间的X解码器。

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