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1. 发明申请

US20100207248A1 Patterns of Semiconductor Device and Method of Forming the Same 有权
标题翻译：半导体器件的形式及其形成方法
公开(公告)号：US20100207248A1
公开(公告)日：2010-08-19
申请号：US12650498
申请日：2009-12-30
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L29/00 , H01L21/308 , H01L21/28
CPC分类号： H01L21/0338 , H01L21/0337
摘要： A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns.
摘要翻译：一种形成半导体器件的图形的方法包括提供一种半导体衬底，该半导体衬底包括将要形成第一图案的第一区域和要形成第二图案的第二区域，每个第二图案的宽度比第一图案宽在所述半导体衬底上形成蚀刻目标层，在所述第一和第二区域的所述蚀刻目标层上形成第一蚀刻图案，在所述第一蚀刻图案的每个的两个侧壁上形成第二蚀刻图案，其中形成在所述第一蚀刻图案中的所述第二蚀刻图案第二区域具有比在第一区域中形成的第二蚀刻图案宽的宽度，去除第一蚀刻图案，在第二区域的蚀刻目标层上形成第三蚀刻图案，第二蚀刻图案与第二图案重叠部分，以及蚀刻使用第三蚀刻图案和第二蚀刻图案作为蚀刻掩模的蚀刻目标层，以形成第一和第二图案。

2. 发明授权

US07696581B2 Isolation film in semiconductor device and method of forming the same 失效
标题翻译：半导体器件中的隔离膜及其形成方法
公开(公告)号：US07696581B2
公开(公告)日：2010-04-13
申请号：US12249130
申请日：2008-10-10
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L21/76224 , H01L27/11526 , H01L27/11531
摘要： The present invention relates to an isolation film in a semiconductor device and method of forming the same. An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the isolation film is thicker than an isolation film of the cell region so that a parasitic transistor is not generated and a leakage current can be prevented.
摘要翻译：本发明涉及一种半导体器件中的隔离膜及其制造方法。隔离膜形成在周边区域的掺杂区域中，其中掺杂区域与单元区域的深阱区域隔离，并且隔离膜比单元区域的隔离膜厚，使得寄生晶体管为不产生并且可以防止泄漏电流。

3. 发明授权

US07183174B2 Flash memory device and method of manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US07183174B2
公开(公告)日：2007-02-27
申请号：US11169893
申请日：2005-06-30
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11526 , H01L27/11529
摘要： A flash memory device and method of manufacturing the same. The flash memory device includes a semiconductor substrate in which a first region where a cell region is formed, a second region where a peripheral region is formed, and a third region formed in the peripheral region at the boundary portion of the cell region and the peripheral region. The device also includes a triple well region formed in the first region and a predetermined region of the third region, an isolation film formed in the first region and having a first depth, an isolation film formed in the second region and having a second depth, which is deeper than the first depth of the isolation film, and a gate oxide film for low voltage and a floating gate, which are stacked on a predetermined region of the first region, a gate oxide film and a gate, which are stacked on a predetermined region of the second region. Additionally, the device includes a dummy flash memory cell in which the floating gate formed in the first region and the gate formed in the second region are separated from each other, and a gate oxide film for high voltage and a gate electrode are stacked on a predetermined region of the third region.
摘要翻译：一种闪存装置及其制造方法。闪速存储器件包括半导体衬底，其中形成有单元区域的第一区域，形成有周边区域的第二区域和形成在单元区域和外围区域的边界部分的外围区域中的第三区域地区。该器件还包括形成在第一区域和第三区域的预定区域中的三阱区域，形成在第一区域中并且具有第一深度的隔离膜，形成在第二区域中并具有第二深度的隔离膜，其比隔离膜的第一深度更深，以及堆叠在第一区域的预定区域上的低电压和浮置栅极氧化膜，栅极氧化物膜和栅极，堆叠在第二区域的预定区域。另外，该装置包括虚拟闪存单元，其中形成在第一区域中的浮置栅极和形成在第二区域中的栅极彼此分离，并且用于高电压的栅极氧化膜和栅电极堆叠在第三区域的预定区域。

4. 发明授权

US06884679B2 Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell 失效
标题翻译：闪存单元及其制造方法和闪存单元的编程/擦除/读取方法
公开(公告)号：US06884679B2
公开(公告)日：2005-04-26
申请号：US10616720
申请日：2003-07-10
申请人： Sung Kee Park , Young Seon You , Yong Wook Kim , Yoo Nam Jeon
发明人： Sung Kee Park , Young Seon You , Yong Wook Kim , Yoo Nam Jeon
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115 , H01L29/7887
摘要： Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.
摘要翻译：公开了一种闪存单元及其制造方法及其编程/擦除/读取方法。闪速存储单元包括形成在半导体衬底的给定区域的第一隧道氧化物膜，形成在第一隧道氧化物膜上的第一浮栅，形成在半导体衬底上并沿着第一浮置区的一个侧壁的第二隧道氧化膜栅极，与第一沟槽氧化膜接触时与第一浮栅隔离的第二浮栅;形成在第一浮栅和第二浮栅上的电介质膜，形成在电介质膜上的控制栅，位于第二隧道氧化膜的一侧以下的半导体衬底，以及形成在第一隧道氧化膜的一侧以下的半导体衬底中的第二结区。因此，本发明可以使用现有的工艺技术来实现高密度的2比特单元或3比特单元。此外，鉴于电荷存储/保持以及编程时间，它可以降低制造成本并实现比传统闪存单元有利的高集成闪存单元。

5. 发明授权

US06821850B2 Method of manufacturing a multi-level flash EEPROM cell 失效
标题翻译：制造多级闪存EEPROM单元的方法
公开(公告)号：US06821850B2
公开(公告)日：2004-11-23
申请号：US10627917
申请日：2003-07-28
申请人： Sang-Hoan Chang , Ki-Seog Kim , Keun-Woo Lee , Sung-Kee Park
发明人： Sang-Hoan Chang , Ki-Seog Kim , Keun-Woo Lee , Sung-Kee Park
IPC分类号： H02L21336
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0425 , G11C2211/5611
摘要： A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.
摘要翻译：提供多级EEPROM单元及其制造方法，以改善多电平单元的程序特性。为此，多级闪速EEPROM单元包括浮置栅极，其通过下面的隧道氧化物层与硅衬底电隔离，形成在浮置栅极的顶部上的第一电介质层，形成在第一控制栅极上的第一控制栅极所述浮置栅极通过所述第一介电层与所述浮置栅极电分离，形成在所述第一控制栅极的侧壁和顶部上的第二介电层，形成在所述第一控制栅极的侧壁和顶部上的第二控制栅极为通过第二电介质层与第一控制栅极电分离，以及在衬底中形成的与第二控制栅极的两个边缘自对准的源极和漏极。

6. 发明授权

US06734458B2 Test pattern for measuring contact resistance and method of manufacturing the same 失效
标题翻译：用于测量接触电阻的测试图案及其制造方法
公开(公告)号：US06734458B2
公开(公告)日：2004-05-11
申请号：US10029390
申请日：2001-12-28
申请人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
发明人： Ki Seog Kim , Young Seon You , Keun Woo Lee , Sung Kee Park
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device. At this time, a first line contact region and a second line contact region are formed between a word line so that a line contact region can form a pair; a plurality of sources are formed in the first line contact region and a plurality of sources are formed in the second line contact region wherein neighboring sources are connected by diffusion layers so that the first line contact region and the second line contact region can be electrically connected; and a plurality of line contact patterns are formed so that the plurality of the sources can be electrically connected by every two in each of the first and second line contact regions wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned. Therefore, the present invention can allow current for measuring the resistance sequentially along the first line contact region and the second line contact region to measure the line contact resistance in which the contact resistance in every source portion is considered.
摘要翻译：本发明涉及一种测量接触电阻的测试图案及其制造方法。为了确认在进行用于制造该器件的实际工艺之前适用于半导体器件的接触电阻，本发明根据实际应用于实际的线路接触的设计规则来设计用于测量接触电阻的测试图案设备。此时，在字线之间形成第一线接触区域和第二线路接触区域，使得线路接触区域可以形成一对; 多个源极形成在第一线路接触区域中，并且多个源极形成在第二线路接触区域中，其中相邻源极通过扩散层连接，使得第一线路接触区域和第二线路接触区域可以电连接 ; 并且形成多个线接触图案，使得多个源可以在形成在第一线接触区域中的线接触图案和线接触图案的第一和第二线路接触区域中的每一个中每两个电连接一次形成在第二线接触区域中的交替位置。因此，本发明可以允许沿着第一线路接触区域和第二线路接触区域依次测量电阻的电流来测量考虑到每个源极部分中的接触电阻的线路接触电阻。

7. 发明授权

US08340397B2 Extensible system and method for stereo matching in real-time 有权
标题翻译：实时立体匹配的可扩展系统和方法
公开(公告)号：US08340397B2
公开(公告)日：2012-12-25
申请号：US11678428
申请日：2007-02-23
申请人： Jae Wook Jeon , Seung Hun Jin , Jung Uk Cho , Sung Kee Park , Munsang Kim , Kyoung Mu Lee , Jong Eun Byun
发明人： Jae Wook Jeon , Seung Hun Jin , Jung Uk Cho , Sung Kee Park , Munsang Kim , Kyoung Mu Lee , Jong Eun Byun
IPC分类号： G06K9/00 , G06K9/56 , G06K9/64 , G03B35/08
CPC分类号： G06K9/32 , G06T7/593 , G06T2207/10021
摘要： Disclosed are a system and a method extensible for performing, in real-time, stereo snatching for calculating depth images with a result of searching for points of similarity by using images taken with two cameras. The system includes a coordinate creating module, a census transform module, a delay XOR calculation module, a stereo matching module, and a control module. Accordingly, by using the system extensible for performing stereo matching, depth information of corrected images can be acquired in real-time without using computer systems or software programs for special purposes. Furthermore, since the system extensible for performing stereo matching can be simply realized by hardware, the system and the method of the present invention can be easily applied to actual intellectual-type robots, industrial settings, etc.
摘要翻译：公开了一种可扩展的系统和方法，用于实时地执行用于计算深度图像的立体声捕获，其结果是通过使用用两个相机拍摄的图像来搜索相似点。该系统包括坐标创建模块，普查变换模块，延迟XOR计算模块，立体匹配模块和控制模块。因此，通过使用可扩展的用于执行立体匹配的系统，可以实时获取校正图像的深度信息，而不用于特殊目的的计算机系统或软件程序。此外，由于用于执行立体匹配的可扩展的系统可以通过硬件简单地实现，所以本发明的系统和方法可以容易地应用于实际的智能机器人，工业设置等。

8. 发明授权

US08252661B2 Method of fabricating flash memory device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US08252661B2
公开(公告)日：2012-08-28
申请号：US12781777
申请日：2010-05-17
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , G11C16/0408 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth.
摘要翻译：半导体器件包括具有单元区域和周边区域的半导体衬底。单元阵列定义在单元区域内，单元阵列具有第一，第二，第三和第四面。第一解码器被限定在外围区域内并且被提供为与单元阵列的第一侧相邻。在设置在电池阵列的第一侧和周边区域之间的第一边界区域处形成第一隔离结构。第一有源区形成在设置在电池阵列的第二侧和周边区域之间的第二边界区域。第一隔离结构具有具有第一深度的第一部分和具有第二深度的第二部分。

9. 发明授权

US08024072B2 Method for self-localization of robot based on object recognition and environment information around recognized object 有权
标题翻译：基于对象识别和识别对象周围环境信息的机器人自定位方法
公开(公告)号：US08024072B2
公开(公告)日：2011-09-20
申请号：US12292715
申请日：2008-11-25
申请人： Sung Kee Park , Soon Yong Park
发明人： Sung Kee Park , Soon Yong Park
IPC分类号： G05B15/00
CPC分类号： B25J19/023 , B25J5/00 , G01C21/00 , G05D1/0251 , G05D1/0274 , G06T7/80 , G06T2207/10021 , G06T2207/30252
摘要： A method for self-localization of a robot, the robot including a camera unit, a database storing a map around a robot traveling path, and a position arithmetic unit estimating the position of the robot, includes: acquiring an image around the robot, in the camera unit. Further, the method includes recognizing, in the position arithmetic unit, an individual object in the image acquired by the camera unit, to generate position values on a camera coordinate system of local feature points of the individual objects and local feature points of a surrounding environment including the individual objects; and estimating, in the position arithmetic unit, the position of the robot on the basis of the map and the position values on the camera coordinate system of local feature points of the individual objects and local feature points of a surrounding environment including the individual objects.
摘要翻译：一种机器人自身定位的方法，包括相机单元的机器人，存储机器人行进路径周围的地图的数据库以及估计机器人的位置的位置运算单元，包括：在机器人周围获取图像，相机单元。此外，该方法包括在位置运算单元中识别由相机单元获取的图像中的单个对象，以在相机坐标系上生成各个对象的局部特征点和周围环境的局部特征点的位置值包括个别物品; 以及在所述位置运算单元中，基于所述映射来估计所述机器人的位置，以及在包括所述各个对象的周围环境的各个对象和所述局部特征点的所述摄像机坐标系上的位置值。

10. 发明申请

US20090210092A1 Method for self-localization of robot based on object recognition and environment information around recognized object 有权
标题翻译：基于对象识别和识别对象周围环境信息的机器人自定位方法
公开(公告)号：US20090210092A1
公开(公告)日：2009-08-20
申请号：US12292715
申请日：2008-11-25
申请人： Sung Kee Park , Soon Yong Park
发明人： Sung Kee Park , Soon Yong Park
IPC分类号： B25J9/00 , B25J19/04
CPC分类号： B25J19/023 , B25J5/00 , G01C21/00 , G05D1/0251 , G05D1/0274 , G06T7/80 , G06T2207/10021 , G06T2207/30252
摘要： A method for self-localization of a robot, the robot including a camera unit, a database storing a map around a robot traveling path, and a position arithmetic unit estimating the position of the robot, includes: acquiring an image around the robot, in the camera unit. Further, the method includes recognizing, in the position arithmetic unit, an individual object in the image acquired by the camera unit, to generate position values on a camera coordinate system of local feature points of the individual objects and local feature points of a surrounding environment including the individual objects; and estimating, in the position arithmetic unit, the position of the robot on the basis of the map and the position values on the camera coordinate system of local feature points of the individual objects and local feature points of a surrounding environment including the individual objects.
摘要翻译：一种机器人自身定位的方法，包括相机单元的机器人，存储机器人行进路径周围的地图的数据库以及估计机器人的位置的位置运算单元，包括：在机器人周围获取图像，相机单元。此外，该方法包括在位置运算单元中识别由相机单元获取的图像中的单个对象，以在相机坐标系上生成各个对象的局部特征点和周围环境的局部特征点的位置值包括个别物品; 以及在所述位置运算单元中，基于所述映射来估计所述机器人的位置，以及在包括所述各个对象的周围环境的各个对象和所述局部特征点的所述摄像机坐标系上的位置值。

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