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1. 发明授权

US06946696B2 Self-aligned isolation double-gate FET 有权
标题翻译：自对准隔离双栅极FET
公开(公告)号：US06946696B2
公开(公告)日：2005-09-20
申请号：US10328285
申请日：2002-12-23
申请人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul Solomon , Min Yang
发明人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul Solomon , Min Yang
IPC分类号： H01L29/417 , H01L21/02 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/762 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786 , H01C27/148
CPC分类号： H01L29/66484 , H01L21/26533 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66772 , H01L29/7831 , H01L29/7834 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。提供了两种降低源极/漏极区下寄生电容的新手段。首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。使用自对准氧植入物或某些其它物种的植入物可以促进氧化。其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。这实现了对背板的低电容，同时保持阈值电压的控制。

2. 发明授权

US07259049B2 Self-aligned isolation double-gate FET 失效
标题翻译：自对准隔离双栅极FET
公开(公告)号：US07259049B2
公开(公告)日：2007-08-21
申请号：US11146624
申请日：2005-06-07
申请人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul M Solomon , Min Yang
发明人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul M Solomon , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L29/66484 , H01L21/26533 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66772 , H01L29/7831 , H01L29/7834 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。提供了两种降低源极/漏极区下寄生电容的新手段。首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。使用自对准氧植入物或某些其它物种的植入物可以促进氧化。其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。这实现了对背板的低电容，同时保持阈值电压的控制。

3. 发明授权

US06365465B1 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06365465B1
公开(公告)日：2002-04-02
申请号：US09272297
申请日：1999-03-19
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L21336
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

4. 发明授权

US06759710B2 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06759710B2
公开(公告)日：2004-07-06
申请号：US10051562
申请日：2002-01-18
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L2976
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

5. 发明授权

US06448131B1 Method for increasing the capacitance of a trench capacitor 失效
标题翻译：增加沟槽电容器电容的方法
公开(公告)号：US06448131B1
公开(公告)日：2002-09-10
申请号：US09929182
申请日：2001-08-14
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , H01L29/66181 , Y10S438/964
摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.
摘要翻译：提供了一种用于增加沟槽电容器表面积的方法。利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。一旦金属沉积在沟槽中，该方法是自限制的。通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

6. 发明授权

US06444578B1 Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权
标题翻译：用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺
公开(公告)号：US06444578B1
公开(公告)日：2002-09-03
申请号：US09791024
申请日：2001-02-21
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译：本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。

7. 发明授权

US07125785B2 Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
标题翻译：混合取向和混合材料绝缘体上半导体晶片
公开(公告)号：US07125785B2
公开(公告)日：2006-10-24
申请号：US10865920
申请日：2004-06-14
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

8. 发明申请

US20080251880A1 MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER 审中-公开
标题翻译：混合方向和混合材料半导体绝缘体波形
公开(公告)号：US20080251880A1
公开(公告)日：2008-10-16
申请号：US12099016
申请日：2008-04-07
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L21/20 , H01L29/04
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

9. 发明授权

US07449767B2 Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
标题翻译：混合取向和混合材料绝缘体上半导体晶片
公开(公告)号：US07449767B2
公开(公告)日：2008-11-11
申请号：US11522905
申请日：2006-09-19
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

10. 发明授权

US09728619B2 Generation of multiple diameter nanowire field effect transistors 有权
公开(公告)号：US09728619B2
公开(公告)日：2017-08-08
申请号：US13610266
申请日：2012-09-11
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/423 , B82Y10/00 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

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