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1. 发明授权

US06444578B1 Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权
标题翻译：用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺
公开(公告)号：US06444578B1
公开(公告)日：2002-09-03
申请号：US09791024
申请日：2001-02-21
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译：本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。

2. 发明授权

US07498640B2 Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby 失效
公开(公告)号：US07498640B2
公开(公告)日：2009-03-03
申请号：US10437930
申请日：2003-05-15
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/119 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

3. 发明授权

US06645861B2 Self-aligned silicide process for silicon sidewall source and drain contacts 失效
标题翻译：用于硅侧壁源极和漏极触点的自对准硅化物工艺
公开(公告)号：US06645861B2
公开(公告)日：2003-11-11
申请号：US09836197
申请日：2001-04-18
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L2144
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译：在具有含硅区域的受控消耗的非平面含硅区域上形成金属硅化物接触的方法（以及由此形成的结构）包括在含硅区域上形成覆盖金属层，在金属上形成硅层层，相对于金属的硅层各向异性地选择性地蚀刻，在第一温度下使金属与硅反应以形成金属硅合金，蚀刻金属层的未反应部分，在第二温度退火以形成金属合金 -Si2，并且选择性地蚀刻未反应的硅层。

4. 发明授权

US06448131B1 Method for increasing the capacitance of a trench capacitor 失效
标题翻译：增加沟槽电容器电容的方法
公开(公告)号：US06448131B1
公开(公告)日：2002-09-10
申请号：US09929182
申请日：2001-08-14
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , H01L29/66181 , Y10S438/964
摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.
摘要翻译：提供了一种用于增加沟槽电容器表面积的方法。利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。一旦金属沉积在沟槽中，该方法是自限制的。通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

5. 发明授权

US06555880B2 Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby 有权
标题翻译：自对准硅化物工艺利用离子植入物降低硅消耗，并控制硅化物形成温度和由此形成的结构
公开(公告)号：US06555880B2
公开(公告)日：2003-04-29
申请号：US09875187
申请日：2001-06-07
申请人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
发明人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
IPC分类号： H01L31119
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L29/41783
摘要： A semiconductor structure includes raised source and drain regions, where the raised source and drain regions are facet free and unconstrained to have a shape conforming to a same crystallographic axes with respect to each other.
摘要翻译：半导体结构包括凸起的源极和漏极区域，其中升高的源极和漏极区域是小面自由的并且不受限制地具有与彼此相同的结晶轴的形状。

6. 发明授权

US06716708B2 Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby 有权
标题翻译：自对准硅化物工艺利用离子植入物降低硅消耗，并控制硅化物形成温度和由此形成的结构
公开(公告)号：US06716708B2
公开(公告)日：2004-04-06
申请号：US10299688
申请日：2002-11-20
申请人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
发明人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L29/41783
摘要： A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译：一种用于在具有所述含硅区域的受控消耗的含硅区域上形成金属硅化物接触的方法（和所得结构）包括将Ge注入含硅区域中，在硅上形成覆盖的金属 - 硅混合物层在第一温度下使金属硅混合物与硅反应以形成金属硅合金，蚀刻金属 - 硅混合物层的未反应部分，在金属硅合金层上形成覆盖硅层，在第二温度下退火温度以形成金属-Si2的合金，并且选择性地蚀刻未反应的硅层。

7. 发明授权

US07102234B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US07102234B2
公开(公告)日：2006-09-05
申请号：US10827064
申请日：2004-04-19
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L23/48 , H01L29/40
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

8. 发明授权

US06809030B2 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06809030B2
公开(公告)日：2004-10-26
申请号：US10185547
申请日：2002-06-28
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

9. 发明授权

US06753606B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US06753606B2
公开(公告)日：2004-06-22
申请号：US09994954
申请日：2001-11-27
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

10. 发明授权

US06503833B1 Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby 有权
标题翻译：自对准硅化物（硅化物）工艺，用于应变硅MOSFET on SiGe和由此形成的结构
公开(公告)号：US06503833B1
公开(公告)日：2003-01-07
申请号：US09712264
申请日：2000-11-15
申请人： Atul Champaklal Ajmera , Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin Kok Chan , Guy Moshe Cohen , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
发明人： Atul Champaklal Ajmera , Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin Kok Chan , Guy Moshe Cohen , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/1054 , H01L29/7834
摘要： A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.
摘要翻译：一种形成半导体衬底（及其结构）的方法，包括在栅极的各个侧面上设置硅化物半导体衬底，该半导体衬底包括形成在其中的源极和漏极，在栅极，源极和漏极区域上沉积金属膜，在第一预定温度下具有Si的金属膜，以形成金属 - 硅合金，蚀刻未反应的金属，在源极漏极和栅极区域上沉积硅膜，在第二预定温度下退火衬底以形成金属-Si2 合金，并选择性地蚀刻未反应的Si。

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