专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080048711A1 ERROR CORRECTING LOGIC SYSTEM 有权
标题翻译：错误修正逻辑系统
公开(公告)号：US20080048711A1
公开(公告)日：2008-02-28
申请号：US11926386
申请日：2007-10-29
申请人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
发明人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
IPC分类号： H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

2. 发明申请

US20060026457A1 Error correcting logic system 有权
标题翻译：错误校正逻辑系统
公开(公告)号：US20060026457A1
公开(公告)日：2006-02-02
申请号：US10710641
申请日：2004-07-27
申请人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
发明人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
IPC分类号： G06F11/00
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

3. 发明申请

US20050012045A1 DETECTOR FOR ALPHA PARTICLE OR COSMIC RAY 失效
标题翻译： ALPHA颗粒或COSMIC RAY的检测器
公开(公告)号：US20050012045A1
公开(公告)日：2005-01-20
申请号：US10604416
申请日：2003-07-18
申请人： John Fifield , Paul Kartschoke , William KIaasen , Stephen Kosonocky , Randy Mann , Jeffery Oppold , Norman Rohrer
发明人： John Fifield , Paul Kartschoke , William KIaasen , Stephen Kosonocky , Randy Mann , Jeffery Oppold , Norman Rohrer
IPC分类号： G01J1/00 , G11C11/412
CPC分类号： G11C11/4125
摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.
摘要翻译：一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。检测电路的第二个应用是传统的逻辑电路。

4. 发明申请

US20070267698A1 DUAL WIRED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双线集成电路板
公开(公告)号：US20070267698A1
公开(公告)日：2007-11-22
申请号：US11774853
申请日：2007-07-09
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
IPC分类号： H01L27/088 , H01L21/84
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
摘要翻译：具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

5. 发明申请

US20050086620A1 METHOD OF REDUCING INSTANTANEOUS CURRENT DRAW AND AN INTEGRATED CIRCUIT MADE THEREBY 失效
标题翻译：减少瞬时电流抽取和集成电路的方法
公开(公告)号：US20050086620A1
公开(公告)日：2005-04-21
申请号：US10605683
申请日：2003-10-17
申请人： Paul Kartschoke , Norman Rohrer
发明人： Paul Kartschoke , Norman Rohrer
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5045
摘要： A method (200, 300, 400, 500) utilizing available timing slack in the various timing paths (108) of a synchronous integrated circuit (104) to reduce the overall instantaneous current draw across the circuit. In the method, each timing path is analyzed to determine its late mode margin or its late mode margin and early mode margin. A delay is added to each timing path having a late mode margin greater than zero. In one embodiment, the delay is equal to the corresponding late mode margin. In another embodiment, the delay is equal to the difference between the corresponding late and early mode margins. Each delay effectively shifts the peak current draw for the corresponding timing path within each clock cycle so that the peaks do not occur simultaneously across all timing paths. In other embodiments, the peak overall instantaneous current draw can be further reduced by reducing the delay in some of the delayed timing paths.
摘要翻译：一种在同步集成电路（104）的各种定时路径（108）中利用可用的定时松弛的方法（200,300,400,500）来减少整个电路上的总瞬时电流消耗。在该方法中，分析每个定时路径以确定其延迟模式余量或其延迟模式余量和早期模式余量。延迟增加到具有大于零的延迟模式余量的每个定时路径。在一个实施例中，延迟等于相应的延迟模式余量。在另一个实施例中，延迟等于相应的延迟和早期模式余量之间的差异。每个延迟有效地移动每个时钟周期内对应的时序路径的峰值电流消耗，使得峰值不会在所有定时路径上同时发生。在其他实施例中，可以通过减少一些延迟定时路径中的延迟来进一步减小峰值总瞬时电流消耗。

6. 发明申请

US20050278662A1 METHOD FOR PREVENTING CIRCUIT FAILURES DUE TO GATE OXIDE LEAKAGE 失效
标题翻译：防止氧化物泄漏导致电路故障的方法
公开(公告)号：US20050278662A1
公开(公告)日：2005-12-15
申请号：US10709798
申请日：2004-05-28
申请人： Paul Kartschoke , Thomas Mitchell , Norman Rohrer , Ronald Rose
发明人： Paul Kartschoke , Thomas Mitchell , Norman Rohrer , Ronald Rose
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.
摘要翻译：公开了一种用于防止由于栅极氧化物泄漏引起的电路故障的方法，并且用于有效地检查芯片上或宏中的电路的许多网络，以便使用DC计算由于栅极氧化物泄漏而发现逻辑故障，其中栅极泄漏为作为电路的静态噪声分析的噪声源。

7. 发明申请

US20050024113A1 METHODS AND APPARATUS FOR EMPLOYING FEEDBACK BODY CONTROL IN CROSS-COUPLED INVERTERS 失效
标题翻译：在交叉耦合逆变器中采用反馈体控制的方法和装置
公开(公告)号：US20050024113A1
公开(公告)日：2005-02-03
申请号：US10604554
申请日：2003-07-30
申请人： Paul Kartschoke , Stephen Kosonocky , Randy Mann , Norman Rohrer
发明人： Paul Kartschoke , Stephen Kosonocky , Randy Mann , Norman Rohrer
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/356104 , H03K3/0375
摘要： In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.
摘要翻译：在第一方面，提供一种交叉耦合的反相器，其包括具有耦合到第一PFET的第一NFET的第一反相器电路和具有耦合到第二PFET的第二NFET的第二反相器电路。第二逆变器电路在多个节点处与第一反相器电路交叉耦合。第一NFET，第二NFET，第一PFET和第二PFET中的至少一个的主体被耦合以形成反馈路径，其减少响应于软错误事件的多个节点中的一个或多个的放电在交叉耦合的逆变器。

8. 发明申请

US20070241398A1 ERROR DETECTION AND CORRECTION IN SEMICONDUCTOR STRUCTURES 有权
标题翻译：半导体结构中的错误检测和校正
公开(公告)号：US20070241398A1
公开(公告)日：2007-10-18
申请号：US11277306
申请日：2006-03-23
申请人： Timothy Dalton , Marc Faucher , Paul Kartschoke , Peter Sandon
发明人： Timothy Dalton , Marc Faucher , Paul Kartschoke , Peter Sandon
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L25/0657 , G01R31/318513 , H01L2225/06513 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.
摘要翻译：半导体结构及其操作方法。半导体结构包括第一半导体芯片和第二半导体芯片。第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。第一和第二半导体芯片包括第一和第二电节点。第二半导体芯片还包括第一比较电路。半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。第一比较电路能够（i）直接从第二电节点接收输入信号，（ii）通过第一耦合通路间接接收来自第一电节点的输入信号，以及（iii）将第一不匹配信号置于对来自第一和第二电节点的输入信号的响应是不同的。

9. 发明申请

US20070192636A1 VOLTAGE DROOP DYNAMIC RECOVERY 失效
标题翻译：电压动态动态恢复
公开(公告)号：US20070192636A1
公开(公告)日：2007-08-16
申请号：US11276101
申请日：2006-02-14
申请人： Christopher Gonzalez , Paul Kartschoke , Vinod Ramadurai , Mathew Ringler
发明人： Christopher Gonzalez , Paul Kartschoke , Vinod Ramadurai , Mathew Ringler
IPC分类号： G06F1/00
CPC分类号： G06F1/28
摘要： Method and systems for dynamically recovering from voltage droops are disclosed. In one embodiment, a microprocessor coupled to a plurality of voltage sensing circuits is provided. The microprocessor includes an instruction sequencing unit and pipeline including a first series of instructions. A central voltage droop detection processor may be coupled to each of the voltage sensing circuits and the microprocessor. Voltage droop is detected using a voltage sensing circuit, after which processing of the microprocessor is interrupted. The pipeline may then be cleared. Subsequently, a second series of instructions including the first series of instructions, and additional instructions are issued. The additional instructions may include stall instructions that cause a delay in processing of the first series of instructions, which prevents re-occurrence of the voltage droop. The interruption and re-issuing also signals the microprocessor that all the data in a particular instruction stream might not be valid and allows recovery.
摘要翻译：公开了用于从电压下降动态恢复的方法和系统。在一个实施例中，提供耦合到多个电压感测电路的微处理器。微处理器包括指令排序单元和包括第一系列指令的流水线。中央电压下降检测处理器可以耦合到每个电压感测电路和微处理器。使用电压检测电路检测电压下降，之后中断微处理器的处理。然后可以清除管道。随后，发出包括第一系列指令和附加指令的第二系列指令。附加指令可以包括导致处理第一系列指令的延迟的停止指令，这防止电压下降的再次发生。中断和重新发出也向微处理器指示特定指令流中的所有数据可能无效并允许恢复。

10. 发明申请

US20050080994A1 METHOD OF DYNAMICALLY CONTROLLING CACHE SIZE 有权
标题翻译：动态控制高速缓存大小的方法
公开(公告)号：US20050080994A1
公开(公告)日：2005-04-14
申请号：US10605616
申请日：2003-10-14
申请人： Erwin Cohen , Thomas Cook , Ian Govett , Paul Kartschoke , Stephen Kosonocky , Peter Sandon , Keith Williams
发明人： Erwin Cohen , Thomas Cook , Ian Govett , Paul Kartschoke , Stephen Kosonocky , Peter Sandon , Keith Williams
IPC分类号： G06F1/32 , G06F12/00 , G06F12/08
CPC分类号： G06F1/3275 , G06F1/3225 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D50/20 , Y10S707/99952
摘要： A power saving cache and a method of operating a power saving cache. The power saving cache includes circuitry to dynamically reduce the logical size of the cache in order to save power. Preferably, a method is used to determine optimal cache size for balancing power and performance, using a variety of combinable hardware and software techniques. Also, in a preferred embodiment, steps are used for maintaining coherency during cache resizing, including the handling of modified (“dirty”) data in the cache, and steps are provided for partitioning a cache in one of several way to provide an appropriate configuration and granularity when resizing.
摘要翻译：省电缓存和操作省电高速缓存的方法。省电高速缓存包括用于动态地减小高速缓存的逻辑大小以节省功率的电路。优选地，使用各种可组合的硬件和软件技术来使用一种方法来确定用于平衡功率和性能的最佳高速缓存大小。此外，在优选实施例中，步骤用于在高速缓存调整大小期间维持一致性，包括对高速缓存中的修改（“脏”）数据的处理，并且提供了用于以多种方式之一对高速缓存进行分区以提供适当配置的步骤调整大小时的粒度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式