专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080048711A1 ERROR CORRECTING LOGIC SYSTEM 有权
标题翻译：错误修正逻辑系统
公开(公告)号：US20080048711A1
公开(公告)日：2008-02-28
申请号：US11926386
申请日：2007-10-29
申请人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
发明人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
IPC分类号： H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

2. 发明申请

US20060026457A1 Error correcting logic system 有权
标题翻译：错误校正逻辑系统
公开(公告)号：US20060026457A1
公开(公告)日：2006-02-02
申请号：US10710641
申请日：2004-07-27
申请人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
发明人： Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
IPC分类号： G06F11/00
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

3. 发明申请

US20050012045A1 DETECTOR FOR ALPHA PARTICLE OR COSMIC RAY 失效
标题翻译： ALPHA颗粒或COSMIC RAY的检测器
公开(公告)号：US20050012045A1
公开(公告)日：2005-01-20
申请号：US10604416
申请日：2003-07-18
申请人： John Fifield , Paul Kartschoke , William KIaasen , Stephen Kosonocky , Randy Mann , Jeffery Oppold , Norman Rohrer
发明人： John Fifield , Paul Kartschoke , William KIaasen , Stephen Kosonocky , Randy Mann , Jeffery Oppold , Norman Rohrer
IPC分类号： G01J1/00 , G11C11/412
CPC分类号： G11C11/4125
摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.
摘要翻译：一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。检测电路的第二个应用是传统的逻辑电路。

4. 发明申请

US20050110535A1 LEAKAGE COMPENSATION CIRCUIT 失效
标题翻译：泄漏补偿电路
公开(公告)号：US20050110535A1
公开(公告)日：2005-05-26
申请号：US10707123
申请日：2003-11-21
申请人： Kerry Bernstein , Anthony Bonaccio , John Fifield , Allen Haar , Shiu Ho , Terence Hook , Michael Sorna , Stephen Wyatt
发明人： Kerry Bernstein , Anthony Bonaccio , John Fifield , Allen Haar , Shiu Ho , Terence Hook , Michael Sorna , Stephen Wyatt
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093
CPC分类号： H03L7/093 , H03L7/0891
摘要： A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.
摘要翻译：一种电路，包括：电容器，耦合在第一电路节点和第二电路节点之间，并且泄漏电流从第一电路节点泄漏到第二电路节点; 以及补偿电路，其适于提供补偿电流以补偿到第一电路节点的漏电流。

5. 发明授权

US07003922B2 Interlocking roof tiles 失效
标题翻译：联锁屋顶瓦
公开(公告)号：US07003922B2
公开(公告)日：2006-02-28
申请号：US10301802
申请日：2002-11-21
申请人： John Fifield
发明人： John Fifield
IPC分类号： E04B1/70
CPC分类号： E04D3/04 , E04D1/16
摘要： An extruded concrete interlocking roof tile has upper and under surfaces, upper and lower edges, two opposite side edges, with the upper surface having a recess extending transversely between the two opposite side edges adjacent the upper edge for receiving a lower edge region of an adjacent tile in overlapping relationship, and in that an integral spacer acts between the recess floor and the undersurface of the adjacent tile.
摘要翻译：挤压混凝土互锁屋顶瓦具有上表面和下表面，上边缘和下边缘，两个相对的侧边缘，上表面具有在邻近上边缘的两个相对侧边之间横向延伸的凹槽，用于接收相邻的下边缘的下边缘区域并且由于整体间隔件作用在相邻瓦片的凹陷地板和下表面之间。

6. 发明申请

US20050162799A1 FUSE LATCH WITH COMPENSATED PROGRAMMABLE RESISTIVE TRIP POINT 有权
标题翻译：具有可补偿可编程电阻点的保险丝锁定
公开(公告)号：US20050162799A1
公开(公告)日：2005-07-28
申请号：US10707963
申请日：2004-01-28
申请人： Darren Anand , John Fifield
发明人： Darren Anand , John Fifield
IPC分类号： G11C17/18 , H02H3/08
CPC分类号： G11C17/18
摘要： A fuse latch circuit with a current reference generator is described where the resistive switch point of the latch is stabilized against effects of manufacturing processing, operating voltage and temperature. A digital control word is used to select the desired resistive trip point of the fuse latch and compensation within the reference generator maintains this resistive trip point with high accuracy. The variable resistive trip point is set to a first value at test and then to a second value in use condition to enhance operating margin, and soft error immunity.
摘要翻译：描述了具有电流参考发生器的保险丝锁存电路，其中闩锁的电阻开关点对制造处理，工作电压和温度的影响是稳定的。使用数字控制字来选择熔丝锁存器的期望电阻跳变点，并且参考发生器内的补偿以高精度维持该电阻跳变点。可变电阻跳变点在测试时被设置为第一个值，然后在使用条件下设置为第二个值，以提高运算裕度和软误差抗扰度。

7. 发明申请

US20050133884A1 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US20050133884A1
公开(公告)日：2005-06-23
申请号：US11051703
申请日：2005-02-04
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

8. 发明申请

US20050122160A1 Method and circuit for compensating for tunneling current 失效
标题翻译：用于补偿隧道电流的方法和电路
公开(公告)号：US20050122160A1
公开(公告)日：2005-06-09
申请号：US10731298
申请日：2003-12-09
申请人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
发明人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/242
摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.
摘要翻译：一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

9. 发明授权

US07716619B2 Design structure for implementing dynamic data path with interlocked keeper and restore devices 失效
标题翻译：用于实现动态数据路径的设计结构，具有互锁的守门员和恢复设备
公开(公告)号：US07716619B2
公开(公告)日：2010-05-11
申请号：US11850691
申请日：2007-09-06
申请人： Geordie Braceras , John Fifield , Harold Pilo
发明人： Geordie Braceras , John Fifield , Harold Pilo
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G11C7/1051 , G06F17/50 , G11C7/1057
摘要： A keeper device design structure for dynamic logic used in integrated circuit designs includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.
摘要翻译：用于集成电路设计中的用于动态逻辑的保持装置设计结构包括静态耦合到动态数据路径的第一保持器路径，第一保持器路径被配置为在其评估期间防止动态数据路径的错误放电，以及第二保持器路径选择性地耦合到动态数据路径。第二保持器路径被配置为在其评估之前将动态数据路径保持在标称预充电水平，其中在评估期间第二保持器路径与动态数据路径解耦。

10. 发明申请

US20080061817A1 Changing Chip Function Based on Fuse States 审中-公开
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20080061817A1
公开(公告)日：2008-03-13
申请号：US11928539
申请日：2007-10-30
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： H03K19/00
CPC分类号： G06F17/5054 , G06F21/76
摘要： Systems, methods, and design structures whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：可以在设备已经离开制造商的控制之后控制电子设备的特定特征的操作和/或访问的系统，方法和设计结构。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式