专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100228806A1 MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY 有权
标题翻译：模块化数字信号处理电路，具有可选择的电路模块之间的专用连接
公开(公告)号：US20100228806A1
公开(公告)日：2010-09-09
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/52 , G06F5/01 , G06F7/00
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

2. 发明授权

US08549055B2 Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry 有权
标题翻译：模块化数字信号处理电路，具有电路模块之间任意可用的专用连接
公开(公告)号：US08549055B2
公开(公告)日：2013-10-01
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

3. 发明授权

US08386550B1 Method for configuring a finite impulse response filter in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中配置有限脉冲响应滤波器的方法
公开(公告)号：US08386550B1
公开(公告)日：2013-02-26
申请号：US11533482
申请日：2006-09-20
申请人： Volker Mauer , Suleyman Sirri Demirsoy
发明人： Volker Mauer , Suleyman Sirri Demirsoy
IPC分类号： G06F17/10
CPC分类号： H03H17/06
摘要： A hybrid FIR filter includes a plurality of FIR filter units arranged as Direct Form FIR filters, connected together in an arrangement similar to a Transpose Form FIR filter. The hybrid filter arrangement may be used to configure a larger FIR filter in a programmable logic device having one or more specialized functional blocks, incorporating multipliers and adders, that are particularly well-suited for configuration as small Direct Form FIR filters.
摘要翻译：混合FIR滤波器包括布置成直接形式FIR滤波器的多个FIR滤波器单元，其以类似于转置形式FIR滤波器的布置连接在一起。混合滤波器布置可以用于在具有一个或多个专用功能块（包括乘法器和加法器）的可编程逻辑器件中配置更大的FIR滤波器，其特别适合于作为小直接形式FIR滤波器的配置。

4. 发明授权

US08291291B1 Data resequencing 有权
标题翻译：数据重新排序
公开(公告)号：US08291291B1
公开(公告)日：2012-10-16
申请号：US12291695
申请日：2008-11-13
申请人： Zhengjun Pan , Suleyman Sirri Demirsoy , Volker Mauer , Kellie Marks
发明人： Zhengjun Pan , Suleyman Sirri Demirsoy , Volker Mauer , Kellie Marks
IPC分类号： G06F11/00
CPC分类号： H03M13/2739 , H03M13/2764 , H03M13/2775 , H03M13/6525 , H03M13/6561 , H04L1/0071
摘要： Interleaving in which functions relating final and original positions are implemented with low complexity using inequalities based on the functions.
摘要翻译：使用基于功能的不等式，以最低复杂度实现关于最终和原始职位的功能的交织。

5. 发明授权

US07260154B1 Method and apparatus for implementing a multiple constraint length Viterbi decoder 有权
标题翻译：用于实现多约束长度维特比解码器的方法和装置
公开(公告)号：US07260154B1
公开(公告)日：2007-08-21
申请号：US10331707
申请日：2002-12-30
申请人： Volker Mauer , Alejandro Diaz-Manero , Martin Langhammer
发明人： Volker Mauer , Alejandro Diaz-Manero , Martin Langhammer
IPC分类号： H04L5/12
CPC分类号： H03M13/4169 , H03M13/3961 , H03M13/41 , H03M13/6508 , H03M13/6516 , H04L1/0054 , H04L1/0059
摘要： A Viterbi decoder capable of decoding a code having a maximum constraint length of Lmax is disclosed. The Viterbi decoder includes an initializer unit that initializes selected states of an encoder during an initial time period to allow the Viterbi decoder to also decode codes having a constraint length less than Lmax.
摘要翻译：公开了一种能够解码最大约束长度为L最大值的码的维特比解码器。维特比解码器包括初始化单元，其在初始时间段期间初始化编码器的选择状态，以允许维特比解码器还解码具有小于最大值的约束长度的码。

6. 发明授权

US06400290B1 Normalization implementation for a logmap decoder 有权
标题翻译：日志对照解码器的规范化实现
公开(公告)号：US06400290B1
公开(公告)日：2002-06-04
申请号：US09511206
申请日：2000-02-23
申请人： Martin Langhammer , Volker Mauer
发明人： Martin Langhammer , Volker Mauer
IPC分类号： H03M1300
CPC分类号： H03M13/3905 , H03M13/6583
摘要： A programmable logic device can be programmed to configure its logic elements to approximate the normalization of probability values used in the operation of logMAP decoders, thereby significantly reducing the amount of logic resources required in the normalization procedure without significantly degrading performance. In the first preferred embodiment, normalization is achieved by approximating the normalization value by calculating an approximate normalization value which is then deducted from all &agr; values in the trellis at any time. This is done by logically ANDing all &agr; input probability values with the NOT of their own MSBs. The resulting outputs are then all bitwise ORed together, the output of which is the approximate normalization value. In another embodiment, the approximate normalization value is calculated using a fixed constant determinable at the outset of the logMAP decoder operation.
摘要翻译：可编程逻辑器件可以配置其逻辑元件来近似在logMAP解码器的操作中使用的概率值的归一化，从而显着减少归一化过程中所需的逻辑资源量，而不会显着降低性能。在第一优选实施例中，通过近似归一化值来实现归一化，即通过计算随后从网格中的所有α值中扣除的近似归一化值。这是通过将所有alpha输入概率值与其自己的MSB的NOT进行逻辑与运算来完成的。所得到的输出随后全部按位或相加在一起，其输出是近似归一化值。在另一个实施例中，使用在logMAP解码器操作开始时可确定的固定常数来计算近似归一化值。

7. 发明授权

US07948267B1 Efficient rounding circuits and methods in configurable integrated circuit devices 有权
标题翻译：可配置集成电路器件中的高效舍入电路和方法
公开(公告)号：US07948267B1
公开(公告)日：2011-05-24
申请号：US12702445
申请日：2010-02-09
申请人： Volker Mauer , Martin Langhammer
发明人： Volker Mauer , Martin Langhammer
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： G06F7/49947
摘要： A specialized processing block for a configurable integrated circuit device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry reuses an adder that is also available, in other configurations, for accumulation of the result. Rounding is performed by adding a constant to the result and then truncating at the bit position at which rounding is desired. The constant may be entered by a user, or may be derived based on a desired rounding method from mask data entered by the user to identify the rounding bit position.
摘要翻译：用于可配置集成电路器件的专用处理块包括用于执行其乘法和和的电路，以及用于舍入结果的电路。舍入电路重新使用加法器，其在其他配置中也可用于积累结果。通过向结果添加常数，然后在需要舍入的位位置截断来执行舍入。常数可以由用户输入，或者可以基于由用户输入的用于识别舍入位位置的掩码数据的期望舍入方法导出。

8. 发明授权

US08620980B1 Programmable device with specialized multiplier blocks 有权
标题翻译：具有专用倍增器块的可编程器件
公开(公告)号：US08620980B1
公开(公告)日：2013-12-31
申请号：US12693614
申请日：2010-01-26
申请人： Volker Mauer , Martin Langhammer
发明人： Volker Mauer , Martin Langhammer
IPC分类号： G06F17/10
CPC分类号： H03H17/0294 , H03H17/0292 , H03H2218/10
摘要： A specialized multiplier block in a programmable device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and output registers to allow chaining of Direct Form II FIR filters into longer Direct Form II FIR filters. An output accumulator also allows the specialized multiplier block to operate as a time-division multiplexed FIR filter, performing several filtering operations during each clock cycle of the programmable device.
摘要翻译：可编程设备中的专用乘法器块包括乘法器和加法器，并且可配置为包括直接形式II FIR滤波器的一种或多种类型的有限脉冲响应（FIR）滤波器。专门的乘法器块还包括输入和输出寄存器，以允许直接形式II FIR滤波器链接到更长的直接形式II FIR滤波器中。输出累加器还允许专用乘法器块作为时分复用FIR滤波器工作，在可编程器件的每个时钟周期期间执行多个滤波操作。

9. 发明授权

US08812576B1 QR decomposition in an integrated circuit device 有权
标题翻译：集成电路设备中的QR分解
公开(公告)号：US08812576B1
公开(公告)日：2014-08-19
申请号：US13229820
申请日：2011-09-12
申请人： Volker Mauer
发明人： Volker Mauer
IPC分类号： G06F7/38
CPC分类号： G06F17/16
摘要： Circuitry for performing QR decomposition of an input matrix includes multiplication/addition circuitry for performing multiplication and addition/subtraction operations on a plurality of inputs, division/square-root circuitry for performing division and square-root operations on an output of the multiplication/addition circuitry, a first memory for storing the input matrix, a second memory for storing a selected vector of the input matrix, and a selector for inputting to the multiplication/addition circuitry any one or more of a vector of the input matrix, the selected vector, and an output of the division/square-root circuitry. On respective successive passes, a respective vector of the input matrix is read from a first memory into a second memory, and elements of a respective vector of an R matrix of the QR decomposition are computed and the respective vector of the input matrix in the first memory is replaced with the respective vector of the R matrix.
摘要翻译：用于执行输入矩阵的QR分解的电路包括用于对多个输入执行乘法和加法/减法运算的乘法/加法电路，用于对乘法/加法的输出执行除法和平方根运算的除法/平方根电路电路，用于存储输入矩阵的第一存储器，用于存储输入矩阵的选定向量的第二存储器，以及用于向乘法/加法电路输入输入矩阵的向量中的一个或多个的选择器，所选择的向量，以及除法/平方根电路的输出。在相应的连续遍中，将输入矩阵的相应向量从第一存储器读取到第二存储器中，并且计算QR分解的R矩阵的相应向量的元素，并且输入矩阵的相应向量在第一存储器存储器被R矩阵的相应矢量代替。

10. 发明授权

US07680233B1 Adaptive sampling rate converter 失效
标题翻译：自适应采样率转换器
公开(公告)号：US07680233B1
公开(公告)日：2010-03-16
申请号：US12061586
申请日：2008-04-02
申请人： Volker Mauer
发明人： Volker Mauer
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03H17/0628 , H03H17/028 , H04L7/0029 , Y10S370/914
摘要： Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value Δμ based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset μ as necessary. Such systems are useful in software defined radio and the like and may be implemented on a variety of devices, including PLDs.
摘要翻译：用于调整采样率转换中使用的相位偏移的装置，方法和技术使用Farrow结构等来补偿时钟问题，例如“时钟抖动”和/或“时钟漂移”效应，这通常在一个时钟是真实的独立于其他。基于跨过渡接口和/或通过缓冲器的时钟域之间的测量数据流，计算相位偏移调整值＆Dgr;μ。在使用输出FIFO缓冲器的情况下，测量的数据流量值表示写入FIFO缓冲器和从FIFO缓冲器读取的数据字的数量，例如存储在FIFO缓冲器中的当前数据字的数量或表示数据字写入FIFO缓冲区。将测量的数据流值与目标数据流值进行比较，其可以是值的范围。相位偏移调整值可以根据需要连续地和/或周期性地更新和/或重新计算并被添加到或从相位偏移μ中减去。这样的系统在软件定义的无线电等中是有用的，并且可以在包括PLD的各种设备上实现。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式