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1. 发明授权

US08549055B2 Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry 有权
标题翻译：模块化数字信号处理电路，具有电路模块之间任意可用的专用连接
公开(公告)号：US08549055B2
公开(公告)日：2013-10-01
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

2. 发明授权

US08291291B1 Data resequencing 有权
标题翻译：数据重新排序
公开(公告)号：US08291291B1
公开(公告)日：2012-10-16
申请号：US12291695
申请日：2008-11-13
申请人： Zhengjun Pan , Suleyman Sirri Demirsoy , Volker Mauer , Kellie Marks
发明人： Zhengjun Pan , Suleyman Sirri Demirsoy , Volker Mauer , Kellie Marks
IPC分类号： G06F11/00
CPC分类号： H03M13/2739 , H03M13/2764 , H03M13/2775 , H03M13/6525 , H03M13/6561 , H04L1/0071
摘要： Interleaving in which functions relating final and original positions are implemented with low complexity using inequalities based on the functions.
摘要翻译：使用基于功能的不等式，以最低复杂度实现关于最终和原始职位的功能的交织。

3. 发明授权

US08386550B1 Method for configuring a finite impulse response filter in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中配置有限脉冲响应滤波器的方法
公开(公告)号：US08386550B1
公开(公告)日：2013-02-26
申请号：US11533482
申请日：2006-09-20
申请人： Volker Mauer , Suleyman Sirri Demirsoy
发明人： Volker Mauer , Suleyman Sirri Demirsoy
IPC分类号： G06F17/10
CPC分类号： H03H17/06
摘要： A hybrid FIR filter includes a plurality of FIR filter units arranged as Direct Form FIR filters, connected together in an arrangement similar to a Transpose Form FIR filter. The hybrid filter arrangement may be used to configure a larger FIR filter in a programmable logic device having one or more specialized functional blocks, incorporating multipliers and adders, that are particularly well-suited for configuration as small Direct Form FIR filters.
摘要翻译：混合FIR滤波器包括布置成直接形式FIR滤波器的多个FIR滤波器单元，其以类似于转置形式FIR滤波器的布置连接在一起。混合滤波器布置可以用于在具有一个或多个专用功能块（包括乘法器和加法器）的可编程逻辑器件中配置更大的FIR滤波器，其特别适合于作为小直接形式FIR滤波器的配置。

4. 发明申请

US20100228806A1 MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY 有权
标题翻译：模块化数字信号处理电路，具有可选择的电路模块之间的专用连接
公开(公告)号：US20100228806A1
公开(公告)日：2010-09-09
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/52 , G06F5/01 , G06F7/00
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

5. 发明授权

US08433976B1 Row column interleavers and deinterleavers with efficient memory usage 有权
标题翻译：行列交错器和解交织器，具有高效的内存使用
公开(公告)号：US08433976B1
公开(公告)日：2013-04-30
申请号：US12768252
申请日：2010-04-27
申请人： Suleyman Sirri Demirsoy
发明人： Suleyman Sirri Demirsoy
IPC分类号： H03M13/00 , G11C29/00 , G06F13/00 , G06F13/28
CPC分类号： H03M13/276 , H03M13/2707 , H03M13/2764 , H03M13/2785 , H03M13/6525
摘要： Interleaver designs and interleaving methods that perform block-wise interleaving by reading blocks into and out of memories, where a block can be written to the memory before another block has finished being read out of the memory, without data clashes, are provided. Corresponding deinterleavers and deinterleaving methods are disclosed.
摘要翻译：交织器设计和交织方法通过将块读入和取出存储器来执行块式交织，其中在没有数据冲突的情况下，在存储器中读出另一个块已经结束之前可将块写入存储器。公开了相应的解交织和解交织方法。

6. 发明授权

US07864080B1 Sample rate conversion by controlled selection of filter outputs 有权
标题翻译：通过控制选择滤波器输出进行采样率转换
公开(公告)号：US07864080B1
公开(公告)日：2011-01-04
申请号：US12345045
申请日：2008-12-29
申请人： Suleyman Sirri Demirsoy , Lawrence Rigby , Benjamin Esposito
发明人： Suleyman Sirri Demirsoy , Lawrence Rigby , Benjamin Esposito
IPC分类号： H03M7/00 , G06F17/17
CPC分类号： H03H17/0685 , H03H17/0275
摘要： A sample rate converter in which filtering is decomposed into phases as permitted by zero padding is described. The outputs of the phases are issued in the correct sequence to provide the resampled sequence.
摘要翻译：描述了一种采样率转换器，其中滤波被零填充所允许的分解成相位。相位的输出以正确的顺序发出以提供重采样序列。

7. 发明授权

US08458243B1 Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering 有权
标题翻译：数字信号处理电路块，支持收缩有限脉冲响应数字滤波
公开(公告)号：US08458243B1
公开(公告)日：2013-06-04
申请号：US12716378
申请日：2010-03-03
申请人： Suleyman Sirri Demirsoy , Hyun Yi
发明人： Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/38 , G06F7/32
CPC分类号： G06F7/5443
摘要： Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.
摘要翻译：集成电路（“IC”）上的数字信号处理（“DSP”）块电路适用于（例如，在IC上的DSP块电路的多个实例中），用于实现有限脉冲响应（“FIR”）数字滤波器收缩形式。每个DSP块可以包括（1）第一和第二乘法器电路和（2）加法电路，用于将（a）乘法器的输出和（b）从DSP块电路的第一其他实例链接的信号相加。为第一乘法器的输出（加法器的上游）或第一乘法器的输入集合中的至少一个提供收缩延迟电路。为加法器的输出提供额外的收缩延迟电路，其被链接到DSP块电路的另一个另外的实例。

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