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1. 发明授权

US08549055B2 Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry 有权
标题翻译：模块化数字信号处理电路，具有电路模块之间任意可用的专用连接
公开(公告)号：US08549055B2
公开(公告)日：2013-10-01
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

2. 发明申请

US20100228806A1 MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY 有权
标题翻译：模块化数字信号处理电路，具有可选择的电路模块之间的专用连接
公开(公告)号：US20100228806A1
公开(公告)日：2010-09-09
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/52 , G06F5/01 , G06F7/00
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

3. 发明授权

US08307023B1 DSP block for implementing large multiplier on a programmable integrated circuit device 有权
标题翻译：用于在可编程集成电路器件上实现大倍数的DSP模块
公开(公告)号：US08307023B1
公开(公告)日：2012-11-06
申请号：US12249051
申请日：2008-10-10
申请人： Wai-Bor Leung , Henry Y. Lui
发明人： Wai-Bor Leung , Henry Y. Lui
IPC分类号： G06F7/523
CPC分类号： G06F7/5324
摘要： A programmable integrated circuit device includes a plurality of specialized processing blocks. Each specialized processing block may be small enough to occupy a single row of logic blocks. The specialized processing blocks may be located adjacent one another in different logic block rows, forming a column of adjacent specialized processing blocks. Each specialized processing block includes one or more multipliers based on carry-save adders whose outputs are combined using compressors. Chain-in and chain-out connections to the compressors allow adjacent specialized processing blocks to be cascaded to form arbitrarily large multipliers. Each specialized processing block also includes a carry-propagate adder, and the carry-propagate added in the final specialized processing block of the chain provides the final result. The size of the multiplication that may be performed is limited only by the number of specialized processing blocks in the programmable integrated circuit device.
摘要翻译：可编程集成电路装置包括多个专用处理块。每个专用处理块可能足够小以占据单行逻辑块。专门的处理块可以在不同的逻辑块行中彼此相邻地定位，形成相邻专用处理块的列。每个专用处理块包括一个或多个基于进位保存加法器的乘法器，其输出使用压缩器组合。与压缩机的连接和链接连接允许相邻的专用处理块级联以形成任意大的乘法器。每个专用处理块还包括进位传播加法器，并且在链的最终专用处理块中添加的进位传播提供最终结果。可执行的乘法大小仅受可编程集成电路器件中的专用处理块的数量的限制。

4. 发明授权

US5394031A Apparatus and method to improve programming speed of field programmable gate arrays 失效
标题翻译：提高现场可编程门阵列编程速度的装置和方法
公开(公告)号：US5394031A
公开(公告)日：1995-02-28
申请号：US163952
申请日：1993-12-08
申请人： Barry K. Britton , Wai-Bor Leung
发明人： Barry K. Britton , Wai-Bor Leung
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17776 , H03K19/17704
摘要： Apparatus and method for compressing configuration bitstreams used to program Field Programmable Gate Arrays (FPGAs) and for decreasing the amount of time necessary to configure FPGAs. In a first embodiment of the present invention, a shift register is employed that enables data bits to be shifted multiple positions per clock cycle through the shift register. As a result, the amount of time required to shift the data bits through the shift register can be reduced by 1/N, where N is the number of positions per clock cycle. The shift register also permits the option of shifting bits through the shift register one bit per clock cycle. In a second embodiment of the present invention, control and address bits are employed to more efficiently manage and reduce the size of the configuration bitstream. Accordingly, one embodiment provides the option of loading data into the array of the FPGA by address column in a non-sequential fashion. In other words, to streamline loading of data into the array from the data shift register, the present invention permits non-sequential writing of frames into the array by column address. Another preferred embodiment of the present invention, permits a previous frame of data (repetitive data) to be loaded into the array without having to resupply the data shift register with the repetitive data. Simple logic control bits indicate how frames of data are to be managed.
摘要翻译：用于压缩用于编程现场可编程门阵列（FPGA）的配置比特流并减少配置FPGA所需的时间量的装置和方法。在本发明的第一实施例中，采用移位寄存器，使移位寄存器能够使每个时钟周期的数据位移位多个位置。结果，通过移位寄存器移动数据位所需的时间量可以减少1 / N，其中N是每个时钟周期的位置数。移位寄存器还允许通过移位寄存器将位移位到每个时钟周期一位。在本发明的第二实施例中，采用控制和地址比特来更有效地管理和减小配置比特流的大小。因此，一个实施例提供了通过地址列以非顺序方式将数据加载到FPGA的阵列中的选项。换句话说，为了简化数据从数据移位寄存器向阵列的加载，本发明允许通过列地址对帧进行非顺序写入阵列。本发明的另一优选实施例允许将前一帧数据（重复数据）加载到阵列中，而不必用重复数据对数据移位寄存器进行补充。简单的逻辑控制位指示如何管理数据帧。

5. 发明授权

US07532646B2 Distributed multiple-channel alignment scheme 有权
标题翻译：分布式多通道校准方案
公开(公告)号：US07532646B2
公开(公告)日：2009-05-12
申请号：US11064477
申请日：2005-02-23
申请人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
发明人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
IPC分类号： H04J3/06 , H04J3/02
CPC分类号： H04L25/14
摘要： A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.
摘要翻译：通道对准电路具有控制器和多个通道对准块。每个通道对齐块同步两个或更多个通道。控制器通过块协调通道的同步，使得（i）两个或更多个块的一个或多个组中的每一个中的信道被同步，并且（ii）每组块独立于任何其他组同步。

6. 发明授权

US06216191B1 Field programmable gate array having a dedicated processor interface 失效
标题翻译：具有专用处理器接口的现场可编程门阵列
公开(公告)号：US06216191B1
公开(公告)日：2001-04-10
申请号：US08950444
申请日：1997-10-15
申请人： Barry K. Britton , Alan Cunningham , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson
发明人： Barry K. Britton , Alan Cunningham , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： A field programmable gate array (FPGA) has an interface circuit that allows signals to be transmitted directly between the FPGA and a processor. The processor interface (PI) of the FPGA enables the processor to access data at any time from either programmable logic of the FPGA or system registers of the PI. The present invention eliminates the need for external intermediate logic previously required to interface an FPGA and a processor.
摘要翻译：现场可编程门阵列（FPGA）具有允许在FPGA和处理器之间直接传输信号的接口电路。 FPGA的处理器接口（PI）可使处理器随时从FPGA的可编程逻辑或PI的系统寄存器访问数据。本发明消除了对FPGA和处理器之间的以前需要的外部中间逻辑的需要。

7. 发明授权

US6043677A Programmable clock manager for a programmable logic device that can implement delay-locked loop functions 失效
标题翻译：可编程逻辑器件的可编程时钟管理器，可实现延迟锁定环路功能
公开(公告)号：US6043677A
公开(公告)日：2000-03-28
申请号：US951128
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： H03K19/177 , H03L7/081 , G06F7/38
CPC分类号： H03K19/1774 , H03L7/0812
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换成至少一个输出时钟，并且PCM可以执行一个或多个延迟锁定环（DLL）功能。在一个实施例中，DLL功能包括时钟延迟，占空比调整和时钟倍增，其中占空比调整可以独立地应用于双倍时钟周期。

8. 发明授权

US6028463A Programmable clock manager for a programmable logic device that can generate at least two different output clocks 失效
标题翻译：可编程逻辑器件的可编程时钟管理器可以生成至少两个不同的输出时钟
公开(公告)号：US6028463A
公开(公告)日：2000-02-22
申请号：US949992
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： G06F1/06 , G06F1/08 , H03K19/173 , H03K19/177 , H03L7/081 , H03L7/089 , H03K7/38
CPC分类号： H03K19/1774 , G06F1/06 , G06F1/08 , H03K19/1733 , H03K19/17704 , H03L7/0812 , H03L7/0891
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换成具有不同时钟速率的至少两个不同的输出时钟。不同的输出时钟可用于控制FPGA内部或外部的不同进程。例如，一个输出时钟可用于控制FPGA的输入/输出寄存器，而第二个更快的输出时钟可用于控制FPGA的内部寄存器。

9. 发明申请

US20060187966A1 Distributed multiple-channel alignment scheme 有权
公开(公告)号：US20060187966A1
公开(公告)日：2006-08-24
申请号：US11064477
申请日：2005-02-23
申请人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
发明人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
IPC分类号： H04J3/06
CPC分类号： H04L25/14
摘要： A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

10. 发明授权

US6060902A Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device 失效
标题翻译：可编程逻辑器件的可编程时钟管理器，可以在不重新配置器件的情况下进行编程
公开(公告)号：US6060902A
公开(公告)日：2000-05-09
申请号：US950448
申请日：1997-10-15
申请人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
发明人： Lucian R. Albu , Barry K. Britton , Wai-Bor Leung , Richard G. Stuby, Jr. , James A. Thompson , Zeljko Zilic
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1774
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换为至少一个输出时钟，并且可以在PLD操作期间对PCM进行编程，而无需重新配置 PLD。

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