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1. 发明申请

US20090108320A1 TUNABLE CAPACITOR 有权
标题翻译： TUNABLE电容器
公开(公告)号：US20090108320A1
公开(公告)日：2009-04-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

2. 发明授权

US09070791B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US09070791B2
公开(公告)日：2015-06-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/漏极区域中的电压条件来选择性地在两个不同的值之间改变电容器所呈现的电容值。或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

3. 发明授权

US07821053B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US07821053B2
公开(公告)日：2010-10-26
申请号：US11560126
申请日：2006-11-15
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

4. 发明申请

US20090101940A1 DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES 审中-公开
标题翻译：用于柔性门阵列设计方法的双门FET结构
公开(公告)号：US20090101940A1
公开(公告)日：2009-04-23
申请号：US11874957
申请日：2007-10-19
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： H01L29/76 , H01L21/82 , G06F17/50
CPC分类号： H03K19/1778 , H01L29/785 , H01L29/78648
摘要： A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be selectively tuned through independent processing of manufacturing parameters to provide an asymmetric circuit response for the device or a symmetric response as dictated by the circuit application.
摘要翻译：适用于标准单元设计方法的门阵列单元或包括双栅极FET器件的可编程门阵列，以在相同单元单元区域内提供一系列性能选项。可以通过制造参数的独立处理来选择性地调节双栅极器件的导电性和驱动强度，以为器件提供不对称电路响应或由电路应用所指示的对称响应。

5. 发明申请

US20080111176A1 TUNABLE CAPACITOR 有权
标题翻译： TUNABLE电容器
公开(公告)号：US20080111176A1
公开(公告)日：2008-05-15
申请号：US11560126
申请日：2006-11-15
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

6. 发明授权

US07619398B2 Programmable on-chip sense line 失效
标题翻译：可编程片上感测线
公开(公告)号：US07619398B2
公开(公告)日：2009-11-17
申请号：US12120255
申请日：2008-05-14
申请人： Corey K. Barrows , Douglas W. Kemerer , Douglas W. Stout , Peter A. Twombly
发明人： Corey K. Barrows , Douglas W. Kemerer , Douglas W. Stout , Peter A. Twombly
IPC分类号： G05F1/40 , H02J13/00 , G05D11/00
CPC分类号： G06F1/26 , Y02P80/14
摘要： Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.
摘要翻译：这里公开了一种用于控制片上配电网络的电源电压的系统。该系统集成了可编程片上感测网络，可在多个位置选择性地连接到配电网络。当感测网络在最佳感测点选择性地连接到配电网络时，产生来自该最佳感测点的局部电压反馈信号并用于调整电源电压，并且因此来管理整个配电网络的电压分布网络。此外，该系统包括用于管理配电网络上的电压分布的策略，用于对配电网络上的压降进行分析的装置以及用于基于策略和配置文件选择最佳感测点的装置。该系统的另一实施例可以进一步控制同一芯片上的多个配电网络的电源电压。

7. 发明授权

US07949978B2 Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit 有权
标题翻译：用于系统架构的结构以及在集成电路中调度片上和跨芯片噪声事件的方法
公开(公告)号：US07949978B2
公开(公告)日：2011-05-24
申请号：US11934804
申请日：2007-11-05
申请人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
发明人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
IPC分类号： G06F17/50 , H03K19/003
CPC分类号： G06F17/505
摘要： A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.
摘要翻译：一种设计结构集成电路（IC）系统架构，其允许通过提供一种方法来减少片上或跨芯片的瞬态噪声预算，以避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件，被披露。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。调度片上噪声事件以避免同时有效的瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者接收多个请求操作的请求; 噪声事件仲裁者确定每个噪声贡献者何时可以基于预先建立的dI / dt预算执行操作; 噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

8. 发明申请

US20080211472A1 PROGRAMMABLE ON-CHIP SENSE LINE 失效
标题翻译：可编程片上感应线
公开(公告)号：US20080211472A1
公开(公告)日：2008-09-04
申请号：US12120255
申请日：2008-05-14
申请人： Corey K. Barrows , Douglas W. Kemerer , Douglas W. Sinut , Peter A. Twombly
发明人： Corey K. Barrows , Douglas W. Kemerer , Douglas W. Sinut , Peter A. Twombly
IPC分类号： G05F1/44
CPC分类号： G06F1/26 , Y02P80/14
摘要： Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.
摘要翻译：这里公开了一种用于控制片上配电网络的电源电压的系统。该系统集成了可编程片上感测网络，可在多个位置选择性地连接到配电网络。当感测网络在最佳感测点选择性地连接到配电网络时，产生来自该最佳感测点的局部电压反馈信号并用于调节电源电压，并且因此来管理整个配电网络网络。此外，该系统包括用于管理配电网络上的电压分布的策略，用于对配电网络上的压降进行分析的装置以及用于基于策略和配置文件选择最佳感测点的装置。该系统的另一实施例可以进一步控制同一芯片上的多个配电网络的电源电压。

9. 发明授权

US08020137B2 Structure for an on-demand power supply current modification system for an integrated circuit 失效
标题翻译：用于集成电路的按需电源电流修改系统的结构
公开(公告)号：US08020137B2
公开(公告)日：2011-09-13
申请号：US11957626
申请日：2007-12-17
申请人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
发明人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.
摘要翻译：用于选择性地将集成电路连接到集成电路外部的元件的电路的设计结构。该电路包括输入/输出元件，其根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚。输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。

10. 发明授权

US07545165B2 System architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit 有权
标题翻译：集成电路中片上和片上噪声事件调度的系统架构和调度方法
公开(公告)号：US07545165B2
公开(公告)日：2009-06-09
申请号：US11621175
申请日：2007-01-09
申请人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
发明人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.
摘要翻译：集成电路（IC）系统架构允许通过提供避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件的手段来减少片上或跨芯片的瞬态噪声预算。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。调度片上噪声事件以避免同时的主动瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者同时接收多个请求操作; 噪声事件仲裁器确定每个噪声分配器何时可以基于预先建立的dI / dt预算来执行操作; 并且噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

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