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1. 发明申请

US20050114054A1 Method for analyzing power supply noise of semiconductor integrated circuit 审中-公开
标题翻译：分析半导体集成电路电源噪声的方法
公开(公告)号：US20050114054A1
公开(公告)日：2005-05-26
申请号：US10988833
申请日：2004-11-16
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
IPC分类号： G06F17/50 , G01R29/26 , H01L21/82 , H01L21/822 , H01L27/04 , H03K17/16
CPC分类号： G01R29/26
摘要： Based on design data of a semiconductor integrated circuit, an impedance related to a power supply wire is calculated, and based on the calculated impedance, a frequency characteristic of power supply noise is analyzed. In calculation of an impedance, an impedance between power supplies which are different in potential, e.g., a main power supply and a ground, may be calculated. Alternatively, an impedance between power supplies which are substantially the same in potential, e.g., a main power supply and an N-well power supply, may be calculated. The calculated impedance includes a wire capacitance between power supply wires, a substrate resistance, an impedance of a package connected to the power supply wires, and so on. Thus, it is possible to provide a method for analyzing power supply noise of a semiconductor integrated circuit, which can be executed at an early stage of a design process with a small amount of calculation.
摘要翻译：基于半导体集成电路的设计数据，计算与电源线相关的阻抗，并且基于所计算的阻抗来分析电源噪声的频率特性。在计算阻抗时，可以计算电位不同的电源之间的阻抗，例如主电源和接地。或者，可以计算电位基本相同的电源之间的阻抗，例如主电源和N阱电源。所计算的阻抗包括电源线之间的线电容，衬底电阻，连接到电源线的封装的阻抗等。因此，可以提供一种用于分析半导体集成电路的电源噪声的方法，其可以在少量计算的设计过程的早期阶段执行。

2. 发明授权

US07278124B2 Design method for semiconductor integrated circuit suppressing power supply noise 有权
标题翻译：半导体集成电路抑制电源噪声的设计方法
公开(公告)号：US07278124B2
公开(公告)日：2007-10-02
申请号：US11024470
申请日：2004-12-30
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063
摘要： An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.
摘要翻译：基于半导体集成电路的设计数据计算电源线的阻抗，获得所计算的阻抗的频率特性，并且基于获得的频率特性改变半导体集成电路的设计。作为上述阻抗，可以计算诸如电源和地之间的电位不同的电源之间的阻抗，或者在诸如电源和N之间的电位基本上相同的电源之间的阻抗 - 可以计算电源。通过设计修改，布线方法，焊盘的数量，电源的分离，封装的类型，电感元件的特性，基板结构，电线之间的距离，去耦电容，电线的长度，并且例如电阻元件的特性被改变。

3. 发明申请

US20050149894A1 Design method for semiconductor integrated circuit suppressing power supply noise 有权
标题翻译：半导体集成电路抑制电源噪声的设计方法
公开(公告)号：US20050149894A1
公开(公告)日：2005-07-07
申请号：US11024470
申请日：2004-12-30
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5036 , G06F17/5063
摘要： An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.
摘要翻译：基于半导体集成电路的设计数据计算电源线的阻抗，获得所计算的阻抗的频率特性，并且基于获得的频率特性改变半导体集成电路的设计。作为上述阻抗，可以计算诸如电源和地之间的电位不同的电源之间的阻抗，或者在诸如电源和N之间的电位基本上相同的电源之间的阻抗 - 可以计算电源。通过设计修改，布线方法，焊盘的数量，电源的分离，封装的类型，电感元件的特性，基板结构，电线之间的距离，去耦电容，电线的长度，并且例如电阻元件的特性被改变。

4. 发明授权

US07225418B2 Operation analyzing method for semiconductor integrated circuit device, analyzing system used in the same, and optimization design method using the same 有权
标题翻译：半导体集成电路器件的运行分析方法，使用的分析系统及其优化设计方法
公开(公告)号：US07225418B2
公开(公告)日：2007-05-29
申请号：US10863231
申请日：2004-06-09
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G01R31/31928
摘要： There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.
摘要翻译：包含通过基于电路信息计算电源端子处的半导体集成电路的每个实例的电压波形并分析各实例的电压波形来形成电压波形信息的步骤，通过以下步骤形成电压抽象信息：抽取电压波形信息，以及基于电压抽象信息计算实例的延迟值的步骤。

5. 发明授权

US07480875B2 Method of designing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路设计方法
公开(公告)号：US07480875B2
公开(公告)日：2009-01-20
申请号：US11312370
申请日：2005-12-21
申请人： Kazuhiro Satoh , Kenji Shimazaki , Takahiro Ichinomiya , Shouzou Hirano
发明人： Kazuhiro Satoh , Kenji Shimazaki , Takahiro Ichinomiya , Shouzou Hirano
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.
摘要翻译：在优化半导体集成电路的必要电容时，可以通过在动态地考虑电池激活率的同时优化IR降（电压降），以更高的精度实现电容优化。换句话说，在估计插入的电源电容以抑制电源的电压波动时，通过在考虑电路中的单元激活率的同时通过减少所需的电容分量作为整体来减少面积，或者通过选择仅在单元操作定时的估计之后补充电源波动较大的时间部分所需的电容。此外，可以在设计的早期的短时间内通过在电容估计时使用布线负载模型来进行该过程。

6. 发明申请

US20060143585A1 Method of designing a semiconductor integrated circuit 失效
公开(公告)号：US20060143585A1
公开(公告)日：2006-06-29
申请号：US11312370
申请日：2005-12-21
申请人： Kazuhiro Satoh , Kenji Shimazaki , Takahiro Ichinomiya , Shouzou Hirano
发明人： Kazuhiro Satoh , Kenji Shimazaki , Takahiro Ichinomiya , Shouzou Hirano
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

7. 发明申请

US20070187777A1 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US20070187777A1
公开(公告)日：2007-08-16
申请号：US11783465
申请日：2007-04-10
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/76 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

8. 发明申请

US20060091550A1 Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same 审中-公开
标题翻译：分析半导体集成电路装置的运行方法，使用的分析装置以及使用其的优化设计方法
公开(公告)号：US20060091550A1
公开(公告)日：2006-05-04
申请号：US11231810
申请日：2005-09-22
申请人： Kenji Shimazaki , Kazuhiro Satoh , Hiroyuki Tsujikawa , Shouzou Hirano , Makoto Nagata
发明人： Kenji Shimazaki , Kazuhiro Satoh , Hiroyuki Tsujikawa , Shouzou Hirano , Makoto Nagata
IPC分类号： H01L23/52
CPC分类号： G06F17/5031
摘要： In a method of analyzing a power noise based on the circuit information of a semiconductor integrated circuit device, the power noise is analyzed in consideration of the influence of the impedance of a substrate. Consequently, the impedance of the substrate which has not been conventionally considered is taken into consideration. Thus, precision in the analysis can be enhanced more greatly.
摘要翻译：在基于半导体集成电路器件的电路信息分析功率噪声的方法中，考虑到衬底的阻抗的影响来分析功率噪声。因此，考虑到未经常考虑的基板的阻抗。因此，分析的精度可以更大的提高。

9. 发明授权

US06959250B1 Method of analyzing electromagnetic interference 失效
标题翻译：分析电磁干扰的方法
公开(公告)号：US06959250B1
公开(公告)日：2005-10-25
申请号：US09615938
申请日：2000-07-13
申请人： Kenji Shimazaki , Hiroyuki Tsujikawa , Seijirou Kojima , Shouzou Hirano
发明人： Kenji Shimazaki , Hiroyuki Tsujikawa , Seijirou Kojima , Shouzou Hirano
IPC分类号： G01R29/08 , G01R23/00 , G01R23/04 , G06F17/50 , H01L29/00
CPC分类号： G06F17/5036 , Y02T10/82
摘要： In contrast with a known dynamic gate-level simulation method, a method of analyzing electromagnetic interference (an EMI analysis method) according to the present invention enables estimation of EMI noise, by means of calculating signal propagation of each node through use of the signal propagation probability technique, and calculating variation time of each node through use of “the Static timing analysis technique”. In short, the present invention is characterized in calculating a frequency characteristic from the relationship between toggle probability of each node and delay in each node.
摘要翻译：与已知的动态门级仿真方法相反，根据本发明的分析电磁干扰（EMI分析方法）的方法能够通过使用信号传播来计算每个节点的信号传播来估计EMI噪声概率技术，并通过使用“静态时序分析技术”来计算每个节点的变化时间。简而言之，本发明的特征在于根据每个节点的触发概率与每个节点的延迟之间的关系来计算频率特性。

10. 发明授权

US06876210B2 Method and apparatus for analyzing electromagnetic interference 失效
标题翻译：用于分析电磁干扰的方法和装置
公开(公告)号：US06876210B2
公开(公告)日：2005-04-05
申请号：US09993595
申请日：2001-11-27
申请人： Kenji Shimazaki , Shouzou Hirano , Tatsuo Ohhashi , Takashi Mizokawa , Hiroyuki Tsujikawa
发明人： Kenji Shimazaki , Shouzou Hirano , Tatsuo Ohhashi , Takashi Mizokawa , Hiroyuki Tsujikawa
IPC分类号： G01R29/08 , G01R31/00 , G01R31/28 , G06F17/50 , H01L21/82 , G01R31/302
CPC分类号： G06F17/5022 , G01R31/002
摘要： A method of analyzing electromagnetic interference in which an amount of electromagnetic interference from an LSI is analyzed, wherein the method includes: an equivalent power source current information calculating step of calculating information of an equivalent power source current flowing in a power source current, from circuit information of the LSI chip; an estimating step of considering at least one of power source information of a power source for supplying a current to the LSI chip, package information of a package for the semiconductor chip, and measurement system information of a measurement system for measuring characteristics of the semiconductor chip, as analysis control information, and of estimating total information in which the analysis control information is reflected in the circuit information, as an equivalent circuit; and a total information analyzing step of performing analysis in accordance with the total information which is estimated in the estimating step.
摘要翻译：一种分析其中分析来自LSI的电磁干扰量的电磁干扰的方法，其中所述方法包括：等效电源电流信息计算步骤，从电路中计算流过电源电流的等效电源电流的信息， LSI芯片的信息; 考虑将用于向LSI芯片提供电流的电源的电源信息，半导体芯片的封装的封装信息以及用于测量半导体芯片的特性的测量系统的测量系统信息中的至少一个的估计步骤作为分析控制信息，并且将分析控制信息反映在电路信息中的总信息估计为等效电路; 以及总信息分析步骤，根据在估计步骤中估计的总信息进行分析。

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