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1. 发明申请

US20070187777A1 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US20070187777A1
公开(公告)日：2007-08-16
申请号：US11783465
申请日：2007-04-10
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/76 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

2. 发明申请

US20050017320A1 Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device 有权
标题翻译：半导体器件的半导体器件图案方法和半导体器件的图案发生器的半导体器件方法
公开(公告)号：US20050017320A1
公开(公告)日：2005-01-27
申请号：US10496297
申请日：2002-11-21
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04 , H01L29/00 , H01L27/108 , H01L29/94
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

3. 发明授权

US07911027B2 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US07911027B2
公开(公告)日：2011-03-22
申请号：US11783465
申请日：2007-04-10
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit.The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

4. 发明授权

US07307333B2 Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device 有权
标题翻译：半导体器件的半导体器件图案方法和半导体器件的图案发生器的半导体器件方法
公开(公告)号：US07307333B2
公开(公告)日：2007-12-11
申请号：US10496297
申请日：2002-11-21
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit.The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

5. 发明授权

US06434730B1 Pattern forming method 有权
标题翻译：图案形成方法
公开(公告)号：US06434730B1
公开(公告)日：2002-08-13
申请号：US09484022
申请日：2000-01-18
申请人： Mitsumi Ito , Hiroyuki Tsujikawa , Seijiro Kojima , Masatoshi Sawada
发明人： Mitsumi Ito , Hiroyuki Tsujikawa , Seijiro Kojima , Masatoshi Sawada
IPC分类号： G06F1750
CPC分类号： H01L23/5223 , G06F17/5068 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： After a layout for a semiconductor device including power and ground lines has been defined, patterns for bypass capacitors, which will be located under the power lines, are created. In this case, a pattern for a semiconductor device, where a bypass capacitor array is inlaid and substrate contacts are located under ground lines, is defined based on design rules input. Next, power lines are extracted and resized. Thereafter, logical operations are performed to place the bypass capacitors and the bypass capacitors are resized. Subsequently, logical operations are performed to define interconnecting diffused layers and the diffused layers are resized. Since the patterns for the power lines have already been defined before the patterns for the bypass capacitors are created, the patterns for the bypass capacitors to be placed under the power lines can be defined automatically. Thus, a pattern for a miniaturized semiconductor device with reduced power supply noise can be created automatically.
摘要翻译：在定义了包括电源和接地线的半导体器件的布局之后，创建将位于电力线下方的用于旁路电容器的图案。在这种情况下，基于设计规则输入来定义用于嵌入旁路电容器阵列并且衬底接触的半导体器件的图案位于地线下方。接下来，提取电源线并调整大小。此后，进行逻辑运算以放置旁路电容器和旁路电容器大小。随后，执行逻辑操作以定义互连扩散层，并且扩散层被调整大小。由于在创建旁路电容器的图案之前已经定义了电源线的图案，因此可以自动定义用于放置在电力线下方的旁路电容器的图案。因此，可以自动地产生具有降低的电源噪声的小型化半导体器件的图案。

6. 外观设计

USD251432S Ice cream freezer 失效
公开(公告)号：USD251432S
公开(公告)日：1979-03-27
申请号：US812006
申请日：1977-06-30
申请人： Masatoshi Sawada , Bruno M. Valbona
设计人： Masatoshi Sawada , Bruno M. Valbona

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