专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090003070A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20090003070A1
公开(公告)日：2009-01-01
申请号：US11869160
申请日：2007-10-09
申请人： Kenji Gomikawa , Kenji Sawamura , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Kenji Sawamura , Mitsuhiro Noguchi
IPC分类号： G11C11/34 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.
摘要翻译：半导体存储器件包括设置在半导体衬底上的存储单元串和包括栅极绝缘膜的第一选择晶体管，该第一选择晶体管包括栅极绝缘膜，该第一选择晶体管设置在半导体衬底上，该半导体衬底的中心部分具有较低的凹部结构，设置有存储单元串的半导体衬底和设置在栅极绝缘膜上的栅电极，第一选择晶体管选择存储单元串。

2. 发明授权

US07636256B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07636256B2
公开(公告)日：2009-12-22
申请号：US11869160
申请日：2007-10-09
申请人： Kenji Gomikawa , Kenji Sawamura , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Kenji Sawamura , Mitsuhiro Noguchi
IPC分类号： G11C16/00
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.
摘要翻译：半导体存储器件包括设置在半导体衬底上的存储单元串和包括栅极绝缘膜的第一选择晶体管，该第一选择晶体管包括栅绝缘膜，该第一选择晶体管包括位于半导体衬底上的半导体衬底，设置有存储单元串的半导体衬底和设置在栅极绝缘膜上的栅电极，第一选择晶体管选择存储单元串。

3. 发明申请

US20090161427A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090161427A1
公开(公告)日：2009-06-25
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

4. 发明授权

US08319316B2 Depletion MOS transistor and enhancement MOS transistor 有权
标题翻译：消耗MOS晶体管和增强型MOS晶体管
公开(公告)号：US08319316B2
公开(公告)日：2012-11-27
申请号：US12788784
申请日：2010-05-27
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
IPC分类号： H01L21/02
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L27/11526 , H01L27/11529 , H01L29/41775 , H01L29/7838
摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
摘要翻译：半导体存储器件包括第一晶体管。第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。沟道区具有第一杂质浓度。源区和漏区具有第二杂质浓度。重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。接触区域具有第四杂质浓度。杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

5. 发明授权

US08093664B2 Non-volatile semiconductor memory device and depletion-type MOS transistor 有权
标题翻译：非易失性半导体存储器件和耗尽型MOS晶体管
公开(公告)号：US08093664B2
公开(公告)日：2012-01-10
申请号：US12359643
申请日：2009-01-26
申请人： Kenji Gomikawa , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Mitsuhiro Noguchi
IPC分类号： H01L29/66
CPC分类号： H01L29/7838 , H01L27/11526 , H01L27/11534
摘要： A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.
摘要翻译：外围电路至少包括第一晶体管。第一晶体管包括通过栅极绝缘膜形成在半导体层的表面上的栅电极。具有第一杂质浓度的第一导电类型的沟道区形成在栅电极正下方和附近的半导体层的表面上。第一导电类型的源极 - 漏极扩散区形成在半导体层的表面上以夹着栅电极，并且具有大于第一杂质浓度的第二杂质浓度。第一导电类型的重叠区域形成在沟道区域和源极 - 漏极扩散区域重叠的栅电极正下方的半导体层的表面上。重叠区域具有大于第二杂质浓度的第三杂质浓度。

6. 发明申请

US20070208903A1 SEMICONDUCTOR DEVICE COMPOSED OF HIGH VOLTAGE TRANSISTORS 有权
标题翻译：由高压晶体管组成的半导体器件
公开(公告)号：US20070208903A1
公开(公告)日：2007-09-06
申请号：US11671138
申请日：2007-02-05
申请人： Kenji Gomikawa , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Mitsuhiro Noguchi
IPC分类号： G06F12/00
CPC分类号： H01L27/11526 , G11C16/0483 , H01L27/115 , H01L27/11529 , Y10S257/905 , Y10S257/908
摘要： A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.
摘要翻译：形成在基板上的多个第一晶体管共享栅电极。隔离区域将多个第一晶体管彼此隔离。在多个第一晶体管的区域中，杂质区域形成为包括多个第一晶体管的源区和漏区，并且杂质区的深度大于源的深度，漏区。杂质区域设定第一晶体管的阈值电压。

7. 发明申请

US20120012909A1 SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER 有权
标题翻译：半导体器件包括具有电荷积累层的存储单元
公开(公告)号：US20120012909A1
公开(公告)日：2012-01-19
申请号：US13241965
申请日：2011-09-23
申请人： Mitsuhiro Noguchi , Kenji Gomikawa
发明人： Mitsuhiro Noguchi , Kenji Gomikawa
IPC分类号： H01L27/115
CPC分类号： G11C16/24 , G11C16/30 , H01L27/0207 , H01L27/0222 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.
摘要翻译：半导体器件包括MOS晶体管，电容器元件，电压产生电路，接触插头和存储单元。 MOS晶体管和电容器元件分别形成在第一元件区域和第二元件区域中。在电压产生电路中，MOS晶体管的电流路径串联连接，并且电容器元件连接到MOS晶体管的源极或漏极。接触插塞形成在源极或漏极上，以连接MOS晶体管或MOS晶体管之一以及电容器元件之一。位于串联连接的最后级的MOS晶体管的栅极和接触插塞之间的距离大于串联连接中位于初始阶段的第二个MOS晶体管的距离。

8. 发明授权

US08049259B2 Semiconductor device including memory cell having charge accumulation layer 有权
标题翻译：包括具有电荷累积层的存储单元的半导体器件
公开(公告)号：US08049259B2
公开(公告)日：2011-11-01
申请号：US12966115
申请日：2010-12-13
申请人： Mitsuhiro Noguchi , Kenji Gomikawa
发明人： Mitsuhiro Noguchi , Kenji Gomikawa
IPC分类号： H01L29/76 , H01L27/108 , H01L29/94 , H01L31/119 , H01L31/113
CPC分类号： G11C16/24 , G11C16/30 , H01L27/0207 , H01L27/0222 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.
摘要翻译：半导体器件包括MOS晶体管，电容器元件，电压产生电路，接触插头和存储单元。 MOS晶体管和电容器元件分别形成在第一元件区域和第二元件区域中。在电压产生电路中，MOS晶体管的电流路径串联连接，并且电容器元件连接到MOS晶体管的源极或漏极。接触插塞形成在源极或漏极上，以连接MOS晶体管或MOS晶体管之一以及电容器元件中的一个。位于串联连接的最后级的MOS晶体管的栅极和接触插塞之间的距离大于串联连接中位于初始阶段的第二个MOS晶体管的距离。

9. 发明申请

US20080001206A1 SEMICONDUCTOR STORAGE DEVICE COMPRISING MIS TRANSISTOR INCLUDING CHARGE STORAGE LAYER 有权
标题翻译：包含MIS晶体管的半导体存储器件，包括充电储存层
公开(公告)号：US20080001206A1
公开(公告)日：2008-01-03
申请号：US11770415
申请日：2007-06-28
申请人： Kenji Gomikawa , Mitsuhiro Noguchi , Takashi Aoi
发明人： Kenji Gomikawa , Mitsuhiro Noguchi , Takashi Aoi
IPC分类号： H01L29/76
CPC分类号： H01L29/7885 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/045
摘要： A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.
摘要翻译：半导体存储器件包括存储单元块。存储单元块包括具有串联连接的电流通道的多个n型第一MIS晶体管。第一MIS晶体管中的每一个包括形成在半导体衬底的（001）面上的源极，漏极和电荷存储层，其间具有栅极绝缘膜，并且被配置为存储数据。在第一MIS晶体管中的每一个中从源极到漏极的方向平行于半导体衬底的[001]方向或[010]方向设置。

10. 发明授权

US08625349B2 Potential relationship in an erasing operation of a nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器的擦除操作中的潜在关系
公开(公告)号：US08625349B2
公开(公告)日：2014-01-07
申请号：US12618200
申请日：2009-11-13
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11521 , H01L27/11526
摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.
摘要翻译：存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式