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1. 发明授权

US08625349B2 Potential relationship in an erasing operation of a nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器的擦除操作中的潜在关系
公开(公告)号：US08625349B2
公开(公告)日：2014-01-07
申请号：US12618200
申请日：2009-11-13
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11521 , H01L27/11526
摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.
摘要翻译：存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

2. 发明授权

US08319316B2 Depletion MOS transistor and enhancement MOS transistor 有权
标题翻译：消耗MOS晶体管和增强型MOS晶体管
公开(公告)号：US08319316B2
公开(公告)日：2012-11-27
申请号：US12788784
申请日：2010-05-27
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
IPC分类号： H01L21/02
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L27/11526 , H01L27/11529 , H01L29/41775 , H01L29/7838
摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
摘要翻译：半导体存储器件包括第一晶体管。第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。沟道区具有第一杂质浓度。源区和漏区具有第二杂质浓度。重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。接触区域具有第四杂质浓度。杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

3. 发明授权

US08400812B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08400812B2
公开(公告)日：2013-03-19
申请号：US13231510
申请日：2011-09-13
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
IPC分类号： G11C5/06 , G11C5/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/063 , G11C8/14 , H01L27/0207 , H01L27/088 , H01L27/11519 , H01L27/11529
摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列和外围电路。存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。外围电路具有晶体管组。晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。

4. 发明申请

US20090161427A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090161427A1
公开(公告)日：2009-06-25
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

5. 发明申请

US20090294824A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090294824A1
公开(公告)日：2009-12-03
申请号：US12412884
申请日：2009-03-27
申请人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.
摘要翻译：第一选择晶体管连接到串联连接的多个存储单元晶体管的一端。第二选择晶体管连接到串联存储单元晶体管的另一端。在半导体衬底中形成第一杂质扩散区，构成第一选择晶体管的第一主电极。在半导体衬底中形成第二杂质扩散区，构成第二选择晶体管的第二主电极。第一杂质扩散区域的深度大于第二杂质扩散区域的深度。

6. 发明授权

US08072020B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08072020B2
公开(公告)日：2011-12-06
申请号：US12412884
申请日：2009-03-27
申请人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.
摘要翻译：第一选择晶体管连接到串联连接的多个存储单元晶体管的一端。第二选择晶体管连接到串联存储单元晶体管的另一端。在半导体衬底中形成第一杂质扩散区，构成第一选择晶体管的第一主电极。在半导体衬底中形成第二杂质扩散区，构成第二选择晶体管的第二主电极。第一杂质扩散区域的深度大于第二杂质扩散区域的深度。

7. 发明授权

US07911844B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07911844B2
公开(公告)日：2011-03-22
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

8. 发明授权

US08604517B2 Non-volatile semiconductor memory device for suppressing deterioration in junction breakdown voltage and surface breakdown voltage of transistor 失效
标题翻译：用于抑制晶体管的结击穿电压和表面击穿电压的劣化的非易失性半导体存储器件
公开(公告)号：US08604517B2
公开(公告)日：2013-12-10
申请号：US13234613
申请日：2011-09-16
申请人： Mitsuhiro Noguchi , Hiroyuki Kutsukake , Masato Endo
发明人： Mitsuhiro Noguchi , Hiroyuki Kutsukake , Masato Endo
IPC分类号： H01L29/66
CPC分类号： H01L27/11524 , H01L27/11519
摘要： According to one embodiment, a non-volatile semiconductor memory device includes a plurality of memory cells and a transistor. The transistor includes a gate insulating film, a gate electrode on the gate insulating film, a sidewall insulating film on both side surfaces of the gate electrode, a source diffusion layer corresponding to the sidewall insulating film, a first hollow formed in a position at a height less than a bottom surface of the gate insulating film directly below an outer side surface of the sidewall insulating film of another side of the gate electrode, a second hollow formed in the first hollow at a position at a height less than the first hollow, and a drain diffusion layer corresponding to another side of the gate electrode and including a low-concentration drain region formed on a bottom surface of the second hollow and a high-concentration drain region.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括多个存储单元和晶体管。晶体管包括栅极绝缘膜，栅极绝缘膜上的栅电极，栅电极的两个侧表面上的侧壁绝缘膜，对应于侧壁绝缘膜的源极扩散层，形成在位于高度小于栅电极另一侧的侧壁绝缘膜的外侧表面正下方的栅极绝缘膜的底表面，在第一中空部分中形成的第二中空在比第一中空部的高度低的位置处，以及与栅电极的另一侧对应的漏极扩散层，并且包括形成在第二中空部的底面上的低浓度漏极区域和高浓度漏极区域。

9. 发明申请

US20090057749A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090057749A1
公开(公告)日：2009-03-05
申请号：US12188617
申请日：2008-08-08
申请人： Kenji GOMIKAWA , Tadashi Iguchi , Mitsuhiro Noguchi , Shoichi Watanabe
发明人： Kenji GOMIKAWA , Tadashi Iguchi , Mitsuhiro Noguchi , Shoichi Watanabe
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.
摘要翻译：存储单元包括浮置栅电极，第一电极间绝缘膜和控制栅电极。外围晶体管包括下电极，第二电极间绝缘膜和上电极。下电极和上电极通过设置在第二电极间绝缘膜上的开口电连接。第一和第二电极间绝缘膜包括高电容率材料，第一电极间绝缘膜具有第一结构，第二电极间绝缘膜具有与第一结构不同的第二结构。

10. 发明申请

US20120037973A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120037973A1
公开(公告)日：2012-02-16
申请号：US13281083
申请日：2011-10-25
申请人： Kenji GOMIKAWA , Tadashi Iguchi , Mitsuhiro Noguchi , Shoichi Watanabe
发明人： Kenji GOMIKAWA , Tadashi Iguchi , Mitsuhiro Noguchi , Shoichi Watanabe
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.
摘要翻译：存储单元包括浮置栅电极，第一电极间绝缘膜和控制栅电极。外围晶体管包括下电极，第二电极间绝缘膜和上电极。下电极和上电极通过设置在第二电极间绝缘膜上的开口电连接。第一和第二电极间绝缘膜包括高电容率材料，第一电极间绝缘膜具有第一结构，第二电极间绝缘膜具有与第一结构不同的第二结构。

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