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1. 发明授权

US08319316B2 Depletion MOS transistor and enhancement MOS transistor 有权
标题翻译：消耗MOS晶体管和增强型MOS晶体管
公开(公告)号：US08319316B2
公开(公告)日：2012-11-27
申请号：US12788784
申请日：2010-05-27
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
IPC分类号： H01L21/02
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L27/11526 , H01L27/11529 , H01L29/41775 , H01L29/7838
摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
摘要翻译：半导体存储器件包括第一晶体管。第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。沟道区具有第一杂质浓度。源区和漏区具有第二杂质浓度。重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。接触区域具有第四杂质浓度。杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

2. 发明申请

US20090294824A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090294824A1
公开(公告)日：2009-12-03
申请号：US12412884
申请日：2009-03-27
申请人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.
摘要翻译：第一选择晶体管连接到串联连接的多个存储单元晶体管的一端。第二选择晶体管连接到串联存储单元晶体管的另一端。在半导体衬底中形成第一杂质扩散区，构成第一选择晶体管的第一主电极。在半导体衬底中形成第二杂质扩散区，构成第二选择晶体管的第二主电极。第一杂质扩散区域的深度大于第二杂质扩散区域的深度。

3. 发明授权

US08072020B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08072020B2
公开(公告)日：2011-12-06
申请号：US12412884
申请日：2009-03-27
申请人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.
摘要翻译：第一选择晶体管连接到串联连接的多个存储单元晶体管的一端。第二选择晶体管连接到串联存储单元晶体管的另一端。在半导体衬底中形成第一杂质扩散区，构成第一选择晶体管的第一主电极。在半导体衬底中形成第二杂质扩散区，构成第二选择晶体管的第二主电极。第一杂质扩散区域的深度大于第二杂质扩散区域的深度。

4. 发明申请

US20110220996A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110220996A1
公开(公告)日：2011-09-15
申请号：US12885031
申请日：2010-09-17
申请人： Hiroyuki KUTSUKAKE , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
发明人： Hiroyuki KUTSUKAKE , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L27/11519 , H01L21/76229 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation insulating film, a source layer, a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The semiconductor substrate is a first conductivity type. The element isolation insulating film divides an upper layer portion of the semiconductor substrate into a plurality of first active regions. The source layer and the drain layer are a second conductivity type and are formed in spaced to each other in an upper portion of each of the first active regions. The gate electrode is provided in a region directly above a channel region on the semiconductor substrate located between the source layer and the drain layer. The gate insulating film is provided between the semiconductor substrate and the gate electrode. The first punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.
摘要翻译：根据一个实施例，半导体器件包括半导体衬底，元件隔离绝缘膜，源极层，漏极层，栅电极，栅极绝缘膜，第一穿通阻挡层和第二穿通塞层。半导体衬底是第一导电类型。元件隔离绝缘膜将半导体衬底的上层部分分成多个第一有源区。源层和漏极层是第二导电类型，并且在每个第一有源区的上部彼此间隔开形成。栅电极设置在位于源层和漏极层之间的半导体衬底上的沟道区的正上方的区域中。栅极绝缘膜设置在半导体衬底和栅电极之间。第一导电类型的第一穿通阻挡层形成在源极的正下方的第一有源区的区域中，并且第一导电类型的第二穿通阻挡层形成在第一有源区的区域中直接在漏极层下面。第一穿通阻止层和第二穿通阻止层各自具有高于半导体衬底的有效杂质浓度。第一穿通阻止层和源极层在沟道区域中分离。第二穿通阻止层和漏极层在沟道区域中分离。

5. 发明授权

US08399953B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08399953B2
公开(公告)日：2013-03-19
申请号：US12885031
申请日：2010-09-17
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
IPC分类号： H01L29/00 , H01L29/167 , H01L21/336
CPC分类号： H01L27/11519 , H01L21/76229 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.
摘要翻译：半导体器件包括半导体衬底，将衬底的上部分成多个第一有源区的元件隔离绝缘膜，源极层和漏极层，栅极电极，栅极绝缘膜，第一穿通阻挡层和第二穿通止挡层。源极层和漏极层在每个第一有源区域的上部彼此间隔开地形成。第一穿通阻挡层形成在源层正下方的第一有源区的区域中，并且第二穿通阻挡层形成在漏极层正下方的第一有源区的区域中。第一穿通阻止层和第二穿通阻止层各自具有高于半导体衬底的有效杂质浓度。第一穿通阻止层和源极层在沟道区域中分离。第二穿通阻止层和漏极层在沟道区域中分离。

6. 发明授权

US08294238B2 Nonvolatile semiconductor memory device with reduced size of peripheral circuit area 有权
标题翻译：非易失性半导体存储器件，外围电路面积减小
公开(公告)号：US08294238B2
公开(公告)日：2012-10-23
申请号：US12765477
申请日：2010-04-22
申请人： Hiroyuki Kutsukake , Takayuki Toba , Yoshiko Kato , Kenji Gomikawa , Haruhiko Koyama
发明人： Hiroyuki Kutsukake , Takayuki Toba , Yoshiko Kato , Kenji Gomikawa , Haruhiko Koyama
IPC分类号： H01L21/70
CPC分类号： H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.
摘要翻译：在存储单元阵列区域周围形成外围电路区域。外围电路区域具有元件区域，隔离元件区域的元件隔离区域和形成在每个元件区域中并包括在沟道宽度方向上延伸的栅电极的场效应晶体管。栅电极的端部和角部位于元件隔离区上。栅电极的角部的曲率半径比从沟道宽度方向的元件区域的端部到沟道宽度方向的栅电极的端部的长度小，并且小于85nm 。

7. 发明授权

US08860121B2 Semiconductor device having upper layer portion of semiconductor substrate divided into a plurality of active areas 有权
标题翻译：半导体器件具有分为多个有源区的半导体衬底的上层部分
公开(公告)号：US08860121B2
公开(公告)日：2014-10-14
申请号：US12725848
申请日：2010-03-17
申请人： Yoshiko Kato , Mitsuhiro Noguchi , Hiroyuki Kutsukake
发明人： Yoshiko Kato , Mitsuhiro Noguchi , Hiroyuki Kutsukake
IPC分类号： H01L29/792 , H01L29/78 , H01L27/115 , H01L29/66 , H01L29/10
CPC分类号： H01L27/11529 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L29/1083 , H01L29/66825
摘要： A semiconductor memory device includes: a semiconductor substrate; a plurality of element isolation insulators disposed in parts of an upper layer portion of the semiconductor substrate and dividing the upper layer portion into a plurality of active areas extended in one direction; tunnel insulating films provided on the active areas: charge storage members provided on the tunnel insulating films; and control gate electrodes provided on the charge storage members. A width of a middle portion of one of the active areas in the up-to-down direction being smaller than a width of a portion of the active areas upper of the middle portion and a width of a portion of the active areas below the middle portion.
摘要翻译：半导体存储器件包括：半导体衬底; 多个元件隔离绝缘体，设置在所述半导体衬底的上层部分的一部分中，并将所述上层部分分成沿一个方向延伸的多个有效区域; 设置在有源区域上的隧道绝缘膜：设置在隧道绝缘膜上的电荷存储构件; 以及设置在电荷存储部件上的控制栅电极。一个有源区域的上下方向的中间部分的宽度小于中间部分的有效区域的一部分的宽度，以及在中间部分之下的有效区域的一部分的宽度一部分。

8. 发明授权

US09070743B2 Semiconductor memory and manufacturing method of the same 有权
标题翻译：半导体存储器及其制造方法相同
公开(公告)号：US09070743B2
公开(公告)日：2015-06-30
申请号：US13413952
申请日：2012-03-07
申请人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
发明人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
IPC分类号： H01L29/788 , H01L21/762 , H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L21/76229 , H01L27/11519 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.
摘要翻译：根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管并且其包括由第二隔离绝缘体围绕的第二有源区。第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

9. 发明授权

US09035370B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09035370B2
公开(公告)日：2015-05-19
申请号：US13415010
申请日：2012-03-08
申请人： Yoshiko Kato , Hiroyuki Kutsukake
发明人： Yoshiko Kato , Hiroyuki Kutsukake
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/11558 , H01L27/11531
摘要： A semiconductor device, includes: a semiconductor substrate; a first conductivity type well and a second conductivity type well; a first active area; a second active area; a first well contact layer; a plurality of first source/drain layers; a first gate insulating film; a first gate electrode; a second well contact layer; a plurality of second source/drain layers; a second gate insulating film; and a second gate electrode. The first well contact layer is formed in the first active area at one end part in the one direction. The one end parts in each of the first active areas and in each of the second active areas are mutually on the same side.
摘要翻译：一种半导体器件，包括：半导体衬底; 第一导电类型井和第二导电类型井; 第一个活跃区域; 第二个活跃区域; 第一阱接触层; 多个第一源极/漏极层; 第一栅极绝缘膜; 第一栅电极; 第二阱接触层; 多个第二源极/漏极层; 第二栅绝缘膜; 和第二栅电极。第一阱接触层在一个方向上的一个端部的第一有源区域中形成。第一有效区域和第二有源区域中的每一个中的一端部分彼此相同。

10. 发明授权

US08698204B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08698204B2
公开(公告)日：2014-04-15
申请号：US13226763
申请日：2011-09-07
申请人： Hiroyuki Kutsukake , Yoshiko Kato
发明人： Hiroyuki Kutsukake , Yoshiko Kato
IPC分类号： H01L27/118 , H01L27/108 , H01L29/76 , H01L23/52 , H01L23/48 , H01L23/40
CPC分类号： H01L27/11524 , H01L27/11519 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor memory device includes a substrate, and device regions in the substrate to extend in a first direction. The device further includes select gates on the substrate to extend in a second direction, and a contact region provided between the select gates and including contact plugs on the respective device regions. The contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. The contact region includes the partial regions of at least two types whose values of N are different. Further, each of the contact plugs has a planar shape of an ellipse, and is arranged so that a major axis of the ellipse is tilted with respect to the first direction.
摘要翻译：在一个实施例中，半导体存储器件包括衬底以及衬底中沿第一方向延伸的器件区域。该装置还包括在基板上沿第二方向延伸的选择栅极以及设置在选择栅极之间并包括各个器件区域上的接触插塞的接触区域。接触区域包括部分区域，其中每个N个接触插塞设置在N个连续的器件区域上，以布置在不平行于第一和第二方向的直线上，其中N是2或更大的整数。接触区域包括N值不同的至少两种类型的部分区域。此外，每个接触插塞具有椭圆形的平面形状，并且被布置成使得椭圆的长轴相对于第一方向倾斜。

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