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1. 发明授权

US08625349B2 Potential relationship in an erasing operation of a nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器的擦除操作中的潜在关系
公开(公告)号：US08625349B2
公开(公告)日：2014-01-07
申请号：US12618200
申请日：2009-11-13
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11521 , H01L27/11526
摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.
摘要翻译：存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

2. 发明授权

US08319316B2 Depletion MOS transistor and enhancement MOS transistor 有权
标题翻译：消耗MOS晶体管和增强型MOS晶体管
公开(公告)号：US08319316B2
公开(公告)日：2012-11-27
申请号：US12788784
申请日：2010-05-27
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
IPC分类号： H01L21/02
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L27/11526 , H01L27/11529 , H01L29/41775 , H01L29/7838
摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
摘要翻译：半导体存储器件包括第一晶体管。第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。沟道区具有第一杂质浓度。源区和漏区具有第二杂质浓度。重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。接触区域具有第四杂质浓度。杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

3. 发明申请

US20090161427A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090161427A1
公开(公告)日：2009-06-25
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

4. 发明申请

US20090294824A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090294824A1
公开(公告)日：2009-12-03
申请号：US12412884
申请日：2009-03-27
申请人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.
摘要翻译：第一选择晶体管连接到串联连接的多个存储单元晶体管的一端。第二选择晶体管连接到串联存储单元晶体管的另一端。在半导体衬底中形成第一杂质扩散区，构成第一选择晶体管的第一主电极。在半导体衬底中形成第二杂质扩散区，构成第二选择晶体管的第二主电极。第一杂质扩散区域的深度大于第二杂质扩散区域的深度。

5. 发明授权

US08072020B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08072020B2
公开(公告)日：2011-12-06
申请号：US12412884
申请日：2009-03-27
申请人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Hiroyuki Kutsukake , Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.
摘要翻译：第一选择晶体管连接到串联连接的多个存储单元晶体管的一端。第二选择晶体管连接到串联存储单元晶体管的另一端。在半导体衬底中形成第一杂质扩散区，构成第一选择晶体管的第一主电极。在半导体衬底中形成第二杂质扩散区，构成第二选择晶体管的第二主电极。第一杂质扩散区域的深度大于第二杂质扩散区域的深度。

6. 发明授权

US07911844B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07911844B2
公开(公告)日：2011-03-22
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

7. 发明申请

US20110220996A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110220996A1
公开(公告)日：2011-09-15
申请号：US12885031
申请日：2010-09-17
申请人： Hiroyuki KUTSUKAKE , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
发明人： Hiroyuki KUTSUKAKE , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L27/11519 , H01L21/76229 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation insulating film, a source layer, a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The semiconductor substrate is a first conductivity type. The element isolation insulating film divides an upper layer portion of the semiconductor substrate into a plurality of first active regions. The source layer and the drain layer are a second conductivity type and are formed in spaced to each other in an upper portion of each of the first active regions. The gate electrode is provided in a region directly above a channel region on the semiconductor substrate located between the source layer and the drain layer. The gate insulating film is provided between the semiconductor substrate and the gate electrode. The first punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.
摘要翻译：根据一个实施例，半导体器件包括半导体衬底，元件隔离绝缘膜，源极层，漏极层，栅电极，栅极绝缘膜，第一穿通阻挡层和第二穿通塞层。半导体衬底是第一导电类型。元件隔离绝缘膜将半导体衬底的上层部分分成多个第一有源区。源层和漏极层是第二导电类型，并且在每个第一有源区的上部彼此间隔开形成。栅电极设置在位于源层和漏极层之间的半导体衬底上的沟道区的正上方的区域中。栅极绝缘膜设置在半导体衬底和栅电极之间。第一导电类型的第一穿通阻挡层形成在源极的正下方的第一有源区的区域中，并且第一导电类型的第二穿通阻挡层形成在第一有源区的区域中直接在漏极层下面。第一穿通阻止层和第二穿通阻止层各自具有高于半导体衬底的有效杂质浓度。第一穿通阻止层和源极层在沟道区域中分离。第二穿通阻止层和漏极层在沟道区域中分离。

8. 发明授权

US08399953B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08399953B2
公开(公告)日：2013-03-19
申请号：US12885031
申请日：2010-09-17
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Norihisa Arai , Tomoaki Hatano
IPC分类号： H01L29/00 , H01L29/167 , H01L21/336
CPC分类号： H01L27/11519 , H01L21/76229 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.
摘要翻译：半导体器件包括半导体衬底，将衬底的上部分成多个第一有源区的元件隔离绝缘膜，源极层和漏极层，栅极电极，栅极绝缘膜，第一穿通阻挡层和第二穿通止挡层。源极层和漏极层在每个第一有源区域的上部彼此间隔开地形成。第一穿通阻挡层形成在源层正下方的第一有源区的区域中，并且第二穿通阻挡层形成在漏极层正下方的第一有源区的区域中。第一穿通阻止层和第二穿通阻止层各自具有高于半导体衬底的有效杂质浓度。第一穿通阻止层和源极层在沟道区域中分离。第二穿通阻止层和漏极层在沟道区域中分离。

9. 发明授权

US08294238B2 Nonvolatile semiconductor memory device with reduced size of peripheral circuit area 有权
标题翻译：非易失性半导体存储器件，外围电路面积减小
公开(公告)号：US08294238B2
公开(公告)日：2012-10-23
申请号：US12765477
申请日：2010-04-22
申请人： Hiroyuki Kutsukake , Takayuki Toba , Yoshiko Kato , Kenji Gomikawa , Haruhiko Koyama
发明人： Hiroyuki Kutsukake , Takayuki Toba , Yoshiko Kato , Kenji Gomikawa , Haruhiko Koyama
IPC分类号： H01L21/70
CPC分类号： H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.
摘要翻译：在存储单元阵列区域周围形成外围电路区域。外围电路区域具有元件区域，隔离元件区域的元件隔离区域和形成在每个元件区域中并包括在沟道宽度方向上延伸的栅电极的场效应晶体管。栅电极的端部和角部位于元件隔离区上。栅电极的角部的曲率半径比从沟道宽度方向的元件区域的端部到沟道宽度方向的栅电极的端部的长度小，并且小于85nm 。

10. 发明授权

US08093664B2 Non-volatile semiconductor memory device and depletion-type MOS transistor 有权
标题翻译：非易失性半导体存储器件和耗尽型MOS晶体管
公开(公告)号：US08093664B2
公开(公告)日：2012-01-10
申请号：US12359643
申请日：2009-01-26
申请人： Kenji Gomikawa , Mitsuhiro Noguchi
发明人： Kenji Gomikawa , Mitsuhiro Noguchi
IPC分类号： H01L29/66
CPC分类号： H01L29/7838 , H01L27/11526 , H01L27/11534
摘要： A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.
摘要翻译：外围电路至少包括第一晶体管。第一晶体管包括通过栅极绝缘膜形成在半导体层的表面上的栅电极。具有第一杂质浓度的第一导电类型的沟道区形成在栅电极正下方和附近的半导体层的表面上。第一导电类型的源极 - 漏极扩散区形成在半导体层的表面上以夹着栅电极，并且具有大于第一杂质浓度的第二杂质浓度。第一导电类型的重叠区域形成在沟道区域和源极 - 漏极扩散区域重叠的栅电极正下方的半导体层的表面上。重叠区域具有大于第二杂质浓度的第三杂质浓度。

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