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1. 发明申请

US20090184344A1 Solid-state image capturing element, method for manufacturing the solid-state image capturing element, and electronic information device 审中-公开
标题翻译：固体摄像元件，固体摄像元件的制造方法以及电子信息装置
公开(公告)号：US20090184344A1
公开(公告)日：2009-07-23
申请号：US12318990
申请日：2009-01-14
申请人： Kenichi Nagai , Noboru Takeuchi , Kazuo Ohtsubo , Yuhji Hara
发明人： Kenichi Nagai , Noboru Takeuchi , Kazuo Ohtsubo , Yuhji Hara
IPC分类号： H01L27/148 , H01L31/0232
CPC分类号： H01L27/14689 , H01L27/14601
摘要： A solid-state image capturing element according to the present invention is provided, in which one or a plurality of light receiving sections for photoelectrically converting an incident light to generate a signal charge is provided on a surface of a semiconductor area or a surface of a semiconductor substrate and a peripheral circuit with a transistor is provided, where a reflection preventing film provided above the light receiving sections and a gate sidewall film of the transistor are formed with a common nitride film that is formed simultaneously.
摘要翻译：提供了根据本发明的固态图像捕获元件，其中在半导体区域或表面上的表面上设置有用于光电转换入射光以产生信号电荷的一个或多个光接收部分提供具有晶体管的半导体衬底和外围电路，其中设置在光接收部分上方的反射防止膜和晶体管的栅极侧壁膜由同时形成的共同氮化物膜形成。

2. 发明申请

US20110151613A1 Solid-state image capturing element, method for manufacturing the solid-state image capturing element, and electronic information device 审中-公开
标题翻译：固体摄像元件，固体摄像元件的制造方法以及电子信息装置
公开(公告)号：US20110151613A1
公开(公告)日：2011-06-23
申请号：US12932297
申请日：2011-02-22
申请人： Kenichi Nagai , Noboru Takeuchi , Kazuo Ohtsubo , Yuhji Hara
发明人： Kenichi Nagai , Noboru Takeuchi , Kazuo Ohtsubo , Yuhji Hara
IPC分类号： H01L31/18
CPC分类号： H01L27/14689 , H01L27/14601
摘要： A solid-state image capturing element according to the present invention is provided, in which one or a plurality of light receiving sections for photoelectrically converting an incident light to generate a signal charge is provided on a surface of a semiconductor area or a surface of a semiconductor substrate and a peripheral circuit with a transistor is provided, where a reflection preventing film provided above the light receiving sections and a gate sidewall film of the transistor are formed with a common nitride film that is formed simultaneously.
摘要翻译：提供了根据本发明的固态图像捕获元件，其中在半导体区域或表面上的表面上设置有用于光电转换入射光以产生信号电荷的一个或多个光接收部分提供具有晶体管的半导体衬底和外围电路，其中设置在光接收部分上方的反射防止膜和晶体管的栅极侧壁膜由同时形成的共同氮化物膜形成。

3. 发明授权

US08106984B2 Image capturing apparatus and electronic information device 有权
标题翻译：图像捕获装置和电子信息装置
公开(公告)号：US08106984B2
公开(公告)日：2012-01-31
申请号：US12379562
申请日：2009-02-25
申请人： Noboru Takeuchi , Kazuo Ohtsubo
发明人： Noboru Takeuchi , Kazuo Ohtsubo
IPC分类号： H04N5/335 , H01L27/00
CPC分类号： H04N5/37457 , H01L27/14603 , H01L27/14612 , H01L27/14641 , H04N5/357
摘要： A solid-state image capturing apparatus includes a pixel array in which a plurality of pixels are arranged in a matrix, where each of the pixels includes: a photodiode for obtaining a signal charge by a photoelectric conversion of an incident light; and an amplifying transistor for the signal charge obtained at the photodiode, and where the amplifying transistor is configured in such a manner that a gate area of the amplifying transistor is defined to be larger than a gate area of other transistors that configure the pixel.
摘要翻译：固体摄像装置包括像素阵列，其中多个像素排列成矩阵，其中每个像素包括：用于通过入射光的光电转换获得信号电荷的光电二极管; 以及用于在光电二极管处获得的信号电荷的放大晶体管，并且其中放大晶体管被配置为使得放大晶体管的栅极面积被定义为大于构成该像素的其它晶体管的栅极区域。

4. 发明申请

US20090219422A1 Image capturing apparatus and electronic information device 有权
标题翻译：图像捕获装置和电子信息装置
公开(公告)号：US20090219422A1
公开(公告)日：2009-09-03
申请号：US12379562
申请日：2009-02-25
申请人： Noboru Takeuchi , Kazuo Ohtsubo
发明人： Noboru Takeuchi , Kazuo Ohtsubo
IPC分类号： H04N5/335
CPC分类号： H04N5/37457 , H01L27/14603 , H01L27/14612 , H01L27/14641 , H04N5/357
摘要： A solid-state image capturing apparatus includes a pixel array in which a plurality of pixels are arranged in a matrix, where each of the pixels includes: a photodiode for obtaining a signal charge by a photoelectric conversion of an incident light; and an amplifying transistor for the signal charge obtained at the photodiode, and where the amplifying transistor is configured in such a manner that a gate area of the amplifying transistor is defined to be larger than a gate area of other transistors that configure the pixel.
摘要翻译：固体摄像装置包括像素阵列，其中多个像素排列成矩阵，其中每个像素包括：用于通过入射光的光电转换获得信号电荷的光电二极管; 以及用于在光电二极管处获得的信号电荷的放大晶体管，并且其中放大晶体管被配置为使得放大晶体管的栅极面积被定义为大于构成该像素的其它晶体管的栅极区域。

5. 发明申请

US20090078974A1 Solid-state image capturing device; manufacturing method for the solid-state image capturing device; and electronic information device 审中-公开
标题翻译：固态摄像装置; 固体摄像装置的制造方法; 和电子信息设备
公开(公告)号：US20090078974A1
公开(公告)日：2009-03-26
申请号：US12229915
申请日：2008-08-28
申请人： Kenichi Nagai , Noboru Takeuchi , Kazuo Ootsubo , Yuji Hara
发明人： Kenichi Nagai , Noboru Takeuchi , Kazuo Ootsubo , Yuji Hara
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14636
摘要： A solid-state image capturing device is provided with a plurality of light receiving elements arranged on a surface section of a semiconductor substrate, a color filter of each color for each of the plurality of light receiving elements, and a plurality of microlenses each for condensing incident light into each of the plurality of light receiving elements, in which the interlayer insulation film is provided directly below the color filter of each color in a state where a passivation and hydrogen sintering process film is removed from the interlayer insulation film.
摘要翻译：固体摄像装置具备配置在半导体衬底的表面部分上的多个光接收元件，多个光接收元件中的每一个的每种颜色的滤色器以及用于冷凝的多个微透镜在从层间绝缘膜去除钝化和氢烧结工艺膜的状态下，将入射光引入到多个光接收元件中的每一个中，其中层间绝缘膜直接设置在每种颜色的滤色器的正下方。

6. 发明申请

US20120104530A1 SUBSTRATE FOR DISPLAY PANEL, AND DISPLAY DEVICE 审中-公开
标题翻译：显示面板基板和显示设备
公开(公告)号：US20120104530A1
公开(公告)日：2012-05-03
申请号：US13378617
申请日：2010-02-18
申请人： Seiji Kaneko , Masahiro Fujiwara , Hiroshi Aichi , Noboru Takeuchi
发明人： Seiji Kaneko , Masahiro Fujiwara , Hiroshi Aichi , Noboru Takeuchi
IPC分类号： H01L27/146
CPC分类号： G06F3/0412 , G02F1/133514 , G02F1/1362 , G02F2001/13312 , G02F2201/52 , G06F3/042 , H01L27/3227 , H01L27/323
摘要： A display panel substrate includes a plurality of pixels, a pixel in the display panel substrate including a PIN diode for conducting therethrough a different electric current in accordance with an amount of light received by the light receiving element, a first inorganic insulating film formed on the PIN diode, a line formed on or above the first inorganic insulating film and electrically connected to the PIN diode, an organic insulating film formed on or above the line, a transparent pixel electrode formed on the organic insulating film, and a transparent cover electrode provided at such a position that the transparent electrode is located between the organic insulating film and the first inorganic insulating film and formed to cover at least a part of an I-layer of the PIN diode.
摘要翻译：显示面板基板包括多个像素，所述显示面板基板中的像素包括PIN二极管，用于根据由所述光接收元件接收的光量而导致不同的电流;第一无机绝缘膜，形成在所述第二无机绝缘膜上; PIN二极管，形成在第一无机绝缘膜上或上方并与PIN二极管电连接的线，形成在线上或上方的有机绝缘膜，形成在有机绝缘膜上的透明像素电极，以及设置有透明盖电极在透明电极位于有机绝缘膜和第一无机绝缘膜之间并形成以覆盖PIN二极管的I层的至少一部分的位置。

7. 发明申请

US20070023792A1 Transistor and transistor manufacturing method 有权
标题翻译：晶体管和晶体管的制造方法
公开(公告)号：US20070023792A1
公开(公告)日：2007-02-01
申请号：US11478854
申请日：2006-07-03
申请人： Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
发明人： Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/266 , H01L21/76224 , H01L21/823481
摘要： In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.
摘要翻译：在本发明的晶体管中，在器件形成区域10的硅衬底101上形成的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离膜110的台阶部分110b的宽度B 隔离膜，并且均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）≤0.2）的关系， / SUP >> 1。通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分硅基板101在器件形成区域的电极均匀部分12中。可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。

8. 发明授权

US07141506B2 Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same 有权
标题翻译：用于评估半导体衬底的性能对平面取向的依赖性的方法和使用其的半导体器件
公开(公告)号：US07141506B2
公开(公告)日：2006-11-28
申请号：US10175076
申请日：2002-06-20
申请人： Tetsuo Endoh , Fujio Masuoka , Noboru Takeuchi , Takuji Tanigami , Takashi Yokoyama
发明人： Tetsuo Endoh , Fujio Masuoka , Noboru Takeuchi , Takuji Tanigami , Takashi Yokoyama
IPC分类号： H01L21/302
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (100); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.
摘要翻译：用于评估半导体衬底的平面取向依赖性的方法包括：在具有平面取向的半导体衬底上形成硬掩模（100）; 使用硬掩模作为掩模对半导体衬底进行各向异性蚀刻，以获得以特定晶体取向的表面; 以及通过使用以特定晶体取向取向的至少一部分表面来评估半导体衬底的平面取向依赖性。

9. 发明授权

US07135726B2 Semiconductor memory and its production process 有权
公开(公告)号：US07135726B2
公开(公告)日：2006-11-14
申请号：US09925952
申请日：2001-08-10
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11568 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10864 , H01L27/11 , H01L27/1104 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

10. 发明授权

US06593231B2 Process of manufacturing electron microscopic sample and process of analyzing semiconductor device 有权
公开(公告)号：US06593231B2
公开(公告)日：2003-07-15
申请号：US10093712
申请日：2002-03-11
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L214763
CPC分类号： G01N23/04
摘要： A process of manufacturing an electron microscopic sample comprising the steps of: (a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration; (b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer; (c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and (d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.

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