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    • 1. 发明申请
      US20070023792A1 Transistor and transistor manufacturing method 有权
    • Transistor and transistor manufacturing method
    • 晶体管和晶体管的制造方法
    • US20070023792A1
    • 2007-02-01
    • US11478854
    • 2006-07-03
    • Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
    • Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
    • H01L21/336 , H01L29/76
    • H01L21/28123 , H01L21/2652 , H01L21/266 , H01L21/76224 , H01L21/823481
    • In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.
    • 在本发明的晶体管中，在器件形成区域10的硅衬底101上形成的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离膜110的台阶部分110b的宽度B 隔离膜，并且均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）≤0.2）的关系， / SUP >> 1。 通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分 硅基板101在器件形成区域的电极均匀部分12中。 可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US07560775B2 Transistor and transistor manufacturing method 有权
    • Transistor and transistor manufacturing method
    • 晶体管和晶体管的制造方法
    • US07560775B2
    • 2009-07-14
    • US11478854
    • 2006-07-03
    • Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
    • Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
    • H01L27/088
    • H01L21/28123 , H01L21/2652 , H01L21/266 , H01L21/76224 , H01L21/823481
    • In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2)0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.
    • 在本发明的晶体管中，在形成在器件形成区域10的硅衬底101上的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离的台阶部分110b的宽度B 膜和均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）2）0.5> 1的关系。 通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分 硅基板101在器件形成区域的电极均匀部分12中。 可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明申请
      US20050141276A1 Semiconductor memory device and production method therefor 审中-公开
    • Semiconductor memory device and production method therefor
    • 半导体存储器件及其制造方法
    • US20050141276A1
    • 2005-06-30
    • US11019474
    • 2004-12-23
    • Noboru Takeuchi , Satoru Yamagata , Shinichi Sato
    • Noboru Takeuchi , Satoru Yamagata , Shinichi Sato
    • H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
    • H01L27/115 , G11C16/0416 , H01L27/11521
    • A semiconductor memory device including: a semiconductor substrate; a plurality of memory cells arranged in a matrix having columns and rows on the semiconductor substrate and each including a source, a drain and a control gate; a plurality of insulative device isolation layers positioned in a surface portion of the substrate as extending in a column direction for isolating the memory cells arranged in each row of the matrix; a plurality of word lines positioned on the substrate as extending in a row direction and each constituted by the control gates of the memory cells of the each row which are connected in series; the source and the drain of each of the memory cells of the each row being positioned in the surface portion of the substrate on opposite sides of a corresponding one of the word lines between an adjacent pair of insulative device isolation layers; and a common source line positioned on the substrate between an adjacent pair of word lines with the intervention of side wall films positioned on side walls of the word lines as extending across the insulative device isolation layers and connecting the sources of the memory cells of the each row in series.
    • 一种半导体存储器件，包括：半导体衬底; 在半导体衬底上布置成具有列和行的矩阵的多个存储单元，每个存储单元包括源极，漏极和控制栅极; 多个绝缘体隔离层，位于基板的表面部分中，沿列方向延伸，用于隔离布置在矩阵的每一行中的存储单元; 位于所述基板上的多个字线，沿着行方向延伸，并且各自由串联连接的各行的存储单元的控制栅极构成; 每行的每个存储单元的源极和漏极位于相邻的一对绝缘器件隔离层之间的对应的一条字线的相对侧上的衬底的表面部分中; 以及位于相邻的一对字线之间的衬底上的公共源极线，其中侧壁膜的介入位于字线的侧壁上，延伸穿过绝缘器件隔离层并连接每个字线的存储器单元的源 排列。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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