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1. 发明授权

US5795803A Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5795803A
公开(公告)日：1998-08-18
申请号：US871680
申请日：1997-06-09
申请人： Yoshiji Takamura , Akio Kawamura , Katsuji Iguchi
发明人： Yoshiji Takamura , Akio Kawamura , Katsuji Iguchi
IPC分类号： H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823892 , H01L27/0922
摘要： A method of manufacturing a semiconductor device comprises; forming a device isolation region in a semiconductor substrate; forming at least a first conductivity type impurity region in the semiconductor substrate; and forming on the semiconductor substrate a transistor including a gate insulating film, a gate electrode, source/drain regions and a channel located directly under the gate electrode, wherein the first conductivity type impurity region is formed by the steps of: an ion implantation 1 having a concentration peak at a location deeper than the bottom of the device isolation region; an ion implantation 2 having a concentration peak at a location around the bottom of the device isolation region; an ion implantation 3 having a concentration peak around the junction regions where the source/drain regions are to be formed; and an ion implantation 4 having a concentration peak on the surface or directly under the surface of the region where the channel is to be formed.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底中形成器件隔离区; 在半导体衬底中形成至少第一导电型杂质区; 以及在所述半导体基板上形成包括栅极绝缘膜，栅极电极，源极/漏极区域和位于所述栅极电极正下方的沟道的晶体管，其中所述第一导电型杂质区域通过以下步骤形成：离子注入1 在比器件隔离区域的底部更深的位置处具有浓度峰值; 离子注入2，其在器件隔离区域的底部周围的位置处具有浓度峰值; 在要形成源/漏区的结区周围具有浓度峰的离子注入3; 以及在要形成沟道的区域的表面或表面下方具有浓度峰值的离子注入4。

2. 发明申请

US20070023792A1 Transistor and transistor manufacturing method 有权
标题翻译：晶体管和晶体管的制造方法
公开(公告)号：US20070023792A1
公开(公告)日：2007-02-01
申请号：US11478854
申请日：2006-07-03
申请人： Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
发明人： Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/266 , H01L21/76224 , H01L21/823481
摘要： In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.
摘要翻译：在本发明的晶体管中，在器件形成区域10的硅衬底101上形成的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离膜110的台阶部分110b的宽度B 隔离膜，并且均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）≤0.2）的关系， / SUP >> 1。通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分硅基板101在器件形成区域的电极均匀部分12中。可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。

3. 发明授权

US07560775B2 Transistor and transistor manufacturing method 有权
标题翻译：晶体管和晶体管的制造方法
公开(公告)号：US07560775B2
公开(公告)日：2009-07-14
申请号：US11478854
申请日：2006-07-03
申请人： Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
发明人： Yoshiji Takamura , Noboru Takeuchi , Satoru Yamagata
IPC分类号： H01L27/088
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/266 , H01L21/76224 , H01L21/823481
摘要： In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2)0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.
摘要翻译：在本发明的晶体管中，在形成在器件形成区域10的硅衬底101上的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离的台阶部分110b的宽度B 膜和均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）2）0.5> 1的关系。通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分硅基板101在器件形成区域的电极均匀部分12中。可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。

4. 发明申请

US20050164439A1 Low volt/high volt transistor 审中-公开
标题翻译：低压/高压晶体管
公开(公告)号：US20050164439A1
公开(公告)日：2005-07-28
申请号：US11071105
申请日：2005-03-04
申请人： Yoshiji Takamura
发明人： Yoshiji Takamura
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/336 , H01L29/76
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process is performed, the low-voltage transistor is subjected to an LDD implantation process. The resultant semiconductor device provides a high-voltage transistor having a deeper LDD region junction depth than the low-voltage transistor, ensuring reliability and performance.
摘要翻译：半导体器件在单个衬底上具有至少一个高电压和低压晶体管。高压晶体管的可靠性通过在进行氧化处理以保护衬底和栅电极之前仅在高压晶体管中进行LDD注入来增强。在执行氧化处理之后，对低压晶体管进行LDD注入工艺。所得到的半导体器件提供具有比低电压晶体管更深的LDD区域结深的高压晶体管，确保可靠性和性能。

5. 发明授权

US06879007B2 Low volt/high volt transistor 失效
公开(公告)号：US06879007B2
公开(公告)日：2005-04-12
申请号：US10214148
申请日：2002-08-08
申请人： Yoshiji Takamura
发明人： Yoshiji Takamura
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process is performed, the low-voltage transistor is subjected to an LDD implantation process. The resultant semiconductor device provides a high-voltage transistor having a deeper LDD region junction depth than the low-voltage transistor, ensuring reliability and performance.

6. 发明授权

US06551871B2 Process of manufacturing a dual gate CMOS transistor 失效
标题翻译：制造双栅极CMOS晶体管的工艺
公开(公告)号：US06551871B2
公开(公告)日：2003-04-22
申请号：US09829068
申请日：2001-04-10
申请人： Yoshiji Takamura
发明人： Yoshiji Takamura
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L29/665 , H01L29/6659
摘要： A process of manufacturing a semiconductor device having a dual gate CMOS transistor in which an nMOS transistor in the dual gate CMOS transistor is formed by the steps of: (a) forming a gate insulating film and a silicon film on a semiconductor substrate; (b) implanting n-type impurities into the silicon film in an nMOS region of the semiconductor substrate; (c) forming a conductive film on the silicon film; and (d) patterning the silicon film and the conductive film into a gate electrode.
摘要翻译：一种制造具有双栅极CMOS晶体管的半导体器件的工艺，其中双栅极CMOS晶体管中的nMOS晶体管通过以下步骤形成：（a）在半导体衬底上形成栅极绝缘膜和硅膜; （b）在半导体衬底的nMOS区域中将n型杂质注入硅膜; （c）在硅膜上形成导电膜; 和（d）将硅膜和导电膜图案化成栅电极。

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