专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5768214A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5768214A
公开(公告)日：1998-06-16
申请号：US689548
申请日：1996-08-09
申请人： Ken Saitoh , Shunichi Sukegawa , Tadashi Tachibana , Makoto Saeki , Yukihide Suzuki
发明人： Ken Saitoh , Shunichi Sukegawa , Tadashi Tachibana , Makoto Saeki , Yukihide Suzuki
IPC分类号： G11C11/41 , G11C7/06 , G11C8/18 , G11C11/409 , G11C8/00
CPC分类号： G11C8/18 , G11C7/06
摘要： A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.
摘要翻译：一种半导体存储器件，其中防止了与输入地址信号的不期望的电平变化有关的错误操作，并且确保了主放大器的适当的操作。半导体存储器件具有主放大器激活脉冲发生器112'，其包括响应灵敏度降低电路10，响应灵敏度选择器12和主放大器激活脉冲发生器14.响应灵敏度降低电路10可以降低响应灵敏度降低电路10的响应灵敏度或输入灵敏度电路112'相对于输入地址转换检测脉冲ATD。响应灵敏度选择器12根据主放大器激活脉冲发生器14的输出状态选择第一输入端子A1或第二输入端子A2。因此，当没有主放大器从主振荡器激活脉冲MA的输出放大器激活脉冲发生器14，响应灵敏度选择器12切换到第一输入端子A1以选择响应灵敏度降低电路10; 当输出主放大器激活脉冲MA时，选择器12切换到第二输入端A2以选择旁路电路11。

2. 发明授权

US5761149A Dynamic RAM 失效
标题翻译：动态RAM
公开(公告)号：US5761149A
公开(公告)日：1998-06-02
申请号：US679724
申请日：1996-07-12
申请人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
发明人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
IPC分类号： H01L27/108 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/418 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/105 , G11C8/00
CPC分类号： G11C29/80 , G11C11/418 , G11C29/83 , G11C8/14 , H01L27/105
摘要： A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.
摘要翻译：动态RAM具有主字线; 多个辅助字线，沿着与主字线交叉的位线的方向排列，多个动态存储单元被连接到该多个辅助字线; 多个副字选择线，其被延伸成与主字线垂直相交，并且通过该多个副字选择线发送用于选择多个辅助字线中的一个的选择信号; 以及用于从主字线接收选择信号的逻辑电路和来自每个辅助字选择线的选择信号，从而形成用于选择一个辅助字线的选择信号。在动态RAM中，当线处于未选择状态时，使主字线和副字选择线中的每一个的电压电平等于地电位。

3. 发明授权

US5805522A Address access path control circuit 失效
标题翻译：地址访问路径控制电路
公开(公告)号：US5805522A
公开(公告)日：1998-09-08
申请号：US706373
申请日：1996-08-30
申请人： Shunichi Sukegawa , Koichi Abe , Makoto Saeki , Yukihide Suzuki
发明人： Shunichi Sukegawa , Koichi Abe , Makoto Saeki , Yukihide Suzuki
IPC分类号： G11C11/413 , G11C7/10 , G11C11/401 , G11C11/408 , G11C11/409 , G11C8/00 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： An address access path control circuit designed for shorter access time and small the layout area with low power consumption and noise. Our control circuit has a latching circuit LMO2A, a main output circuit MO3, and a common-bus driving circuit CBD for holding the level of a pair of common-buses CB/CB.sub.-- at the ground level during a prescribed period of time in which address transition takes place while the read data is output to common-buses CB/CB.sub.-- at a timing corresponding to the address signal. A data output buffer DO-BUF outputs to the outside the data transmitted from common-buses CB/CB.sub.-- to data output lines OD/OD.sub.-- in response to the input of control signal DOE. A control signal DOE is input to data output buffer DO-BUF during the period in which data output lines OD/OD.sub.-- are at the ground level.
摘要翻译：一种地址访问路径控制电路，设计用于更短的访问时间，并且具有低功耗和噪声的布局区域较小。我们的控制电路有一个锁存电路LMO2A，一个主输出电路MO3和一个共用总线驱动电路CBD，用于在一段规定的时间内保持一对公共汽车CB / CB-的电平，在与地址信号相对应的定时将读取数据输出到公共总线CB / CB-时发生地址转换。响应于控制信号DOE的输入，数据输出缓冲器DO-BUF向外部输出从公共总线CB / CB-发送到数据输出线OD / OD-的数据。在数据输出线OD / OD-处于地电平的期间，控制信号DOE输入到数据输出缓冲器DO-BUF。

4. 发明授权

US5844915A Method for testing word line leakage in a semiconductor memory device 失效
标题翻译：在半导体存储器件中测试字线泄漏的方法
公开(公告)号：US5844915A
公开(公告)日：1998-12-01
申请号：US716080
申请日：1996-09-19
申请人： Yoritaka Saitoh , Shunichi Sukegawa , Makoto Saeki , Yukihide Suzuki
发明人： Yoritaka Saitoh , Shunichi Sukegawa , Makoto Saeki , Yukihide Suzuki
IPC分类号： G11C11/401 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/50 , G11C29/56
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C11/401
摘要： A word line leak check test for a semiconductor memory arranged as a matrix which includes word lines and y-selection lines. First, a RAS signal is enabled while a prescribed row address is input, and word line 22 is driven to the Vpp level. Then, when the CAS signal is enabled, the voltage source is disconnected from word line 22, and word line 22 floats. Two bits for the column address are disregarded, and the Y selection signal line 23 is decoded without those 2 bits. By this means, 4 y-selection signal lines 23 are simultaneously enabled. When this condition has been maintained for a prescribed time T, a delayed write operation is conducted, and then it is determined whether the data has been correctly stored in memory cell 24.
摘要翻译：布置为包括字线和y选择线的矩阵的半导体存储器的字线泄漏检查测试。首先，在输入规定的行地址的同时使能RAS信号，将字线22驱动到Vpp电平。然后，当CAS信号被使能时，电压源与字线22断开，字线22浮起。忽略列地址的两位，并且Y选择信号线23被解码而没有那些2位。通过这种方式，同时使能4个y选择信号线23。当该条件保持规定时间T时，进行延迟写入操作，然后确定数据是否已被正确存储在存储单元24中。

5. 发明授权

US5831910A Semiconductor integrated circuit utilizing overdriven differential amplifiers 失效
标题翻译：采用过驱动差分放大器的半导体集成电路
公开(公告)号：US5831910A
公开(公告)日：1998-11-03
申请号：US689989
申请日：1996-08-16
申请人： Yukihide Suzuki , Noriaki Kubota , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
发明人： Yukihide Suzuki , Noriaki Kubota , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/065 , G11C7/06
摘要： A semiconductor integrated circuit is provided in which a differential amplifier circuit such as a sense amplifier is operated at high speed even if the operating voltage is reduced. To achieve this, a MOS transistor for supplying the operating voltage to a drive line on the high-potential side of a differential amplifier circuit is of N-channel type and the amplitude of a switching control signal for controlling this transistor is the potential of the step-up voltage produced by stepping up a supply voltage in level. The output voltage of an internal step-up circuit for achieving a word-line selection level is utilizable as the step-up voltage.
摘要翻译：提供了一种半导体集成电路，其中诸如读出放大器的差分放大器电路即使在工作电压降低的情况下也以高速运行。为了实现这一点，用于向差分放大器电路的高电位侧的驱动线提供工作电压的MOS晶体管是N沟道型，并且用于控制该晶体管的开关控制信号的幅度是通过提高电源电压而产生的升压电压。用于实现字线选择电平的内部升压电路的输出电压可用作升压电压。

6. 发明授权

US5764580A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5764580A
公开(公告)日：1998-06-09
申请号：US689921
申请日：1996-08-16
申请人： Yukihide Suzuki , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
发明人： Yukihide Suzuki , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
IPC分类号： G11C7/06 , G11C7/22 , G11C7/00
CPC分类号： G11C7/065 , G11C7/22
摘要： A semiconductor integrated circuit capable of preventing the excessive overdriving of sense amplifiers when the supply voltage fed thereto is raised. The integrated circuit has differential amplifiers for amplifying a potential difference on complementary signal lines, and a control circuit for generating a first driving control signal for supplying the differential amplifiers with a first driving voltage as an overdriving power supply therefor. The control circuit further generates a second driving control signal for supplying the differential amplifiers with a second driving voltage which is activated after the activated first driving control signal is deactivated and which is lower in level than the first driving voltage. The control circuit includes a MOS circuit as a delay circuit composed of MOS transistors for defining a time interval from the time the first driving control signal is activated until the second driving control signal is activated. With this arrangement, the period during which the overdriving voltage is applied is variable in dependence on the level of the supply voltage such that the overdrive period is relatively short if the supply voltage is high and relatively long if the supply voltage is low.
摘要翻译：一种半导体集成电路，其能够在提供供给电压时防止读出放大器的过度驱动。集成电路具有用于放大互补信号线上的电位差的差分放大器，以及用于产生第一驱动控制信号的控制电路，用于向差分放大器提供第一驱动电压作为过驱动电源。控制电路还产生第二驱动控制信号，用于向差分放大器提供第二驱动电压，该第二驱动电压在激活的第一驱动控制信号被去激活之后被激活，并且其电位低于第一驱动电压。控制电路包括作为由MOS晶体管组成的延迟电路的MOS电路，用于定义从第一驱动控制信号激活直到第二驱动控制信号被激活的时间间隔。通过这种布置，施加过驱动电压的周期可以根据电源电压的电平而变化，使得如果电源电压较高并且如果电源电压低，则过驱动周期相对较短。

7. 发明授权

US5557580A Word line driving circuit 失效
标题翻译：字线驱动电路
公开(公告)号：US5557580A
公开(公告)日：1996-09-17
申请号：US292452
申请日：1994-08-18
申请人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
发明人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
IPC分类号： G11C11/407 , G11C8/08 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C8/00 , G11C7/00
CPC分类号： G11C8/08
摘要： A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.
摘要翻译：一种字线驱动电路，通过使字线驱动器的布局面积小，能够有效地防止字线放电期间的接地噪声，同时容纳字线中的音调变窄。字线驱动电路包括n型MOS晶体管14和p型MOS晶体管12. n型MOS晶体管14的漏极端子和字线驱动器10中的p型MOS晶体管12的漏极端子连接到基极字线WLi的终端。输出晶体管驱动电路16的输出端子与p型MOS晶体管12的源极端子连接，第一输出晶体管控制电路18的输出端子与栅极端子连接。第二输出晶体管控制电路20的输出端子与n型MOS晶体管14的栅极端子连接，作为引导电流的基准电位端子的接地端子22与源极端子连接。

8. 发明授权

US5862086A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US5862086A
公开(公告)日：1999-01-19
申请号：US701348
申请日：1996-08-22
申请人： Chisa Makimura , Yukihide Suzuki , Shunichi Sukegawa , Hiroyuki Fujiwara , Masayuki Hira
发明人： Chisa Makimura , Yukihide Suzuki , Shunichi Sukegawa , Hiroyuki Fujiwara , Masayuki Hira
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/785 , G11C29/804 , G11C29/808
摘要： A semiconductor storage device is provided with a storage circuit for a faulty address and a plurality of redundant word lines corresponding to the storage circuit. The storage circuit is adapted to store a faulty address required for selecting a redundant word line. The faulty address is compared with an address input at the time of memory access by a comparator. Using a coincidence signal produced from the comparator and a predetermined address signal contained in the input address, a defect relief circuit selects one of the redundant word lines in place of the faulty word line.
摘要翻译：半导体存储装置具有用于故障地址的存储电路和对应于存储电路的多个冗余字线。存储电路适于存储选择冗余字线所需的故障地址。故障地址与比较器存储器访问时的地址输入进行比较。使用从比较器产生的符合信号和包含在输入地址中的预定地址信号，缺陷消除电路选择一个冗余字线来代替有缺陷的字线。

9. 发明授权

US06282141B1 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US06282141B1
公开(公告)日：2001-08-28
申请号：US09571512
申请日：2000-05-15
申请人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
发明人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
IPC分类号： G11C800
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1051 , G11C11/406 , G11C11/40626 , G11C11/4096
摘要： Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.
摘要翻译：根据特定写入操作模式的指定，同时选择不同存储器阵列中的两个存储器单元，以将写入信号的逻辑1与每个电容器中存在电荷的状态相关联。此外，写入信号的逻辑0与在电容器中不存在电荷以写入相同写入信号的状态相关联。根据特定读取操作模式的指定，同时选择不同存储器阵列中的两个动态存储单元，以将每个动态存储单元的电容器中存在电荷的状态与读取信号的逻辑1和关联响应于写入操作，具有读取信号的逻辑0的电容器中不存在电荷的状态。因此，优先输出两个读取信号的逻辑1。

10. 发明授权

US6064605A Semiconductor memory device and memory system 有权
公开(公告)号：US6064605A
公开(公告)日：2000-05-16
申请号：US395158
申请日：1999-09-14
申请人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
发明人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
IPC分类号： G11C11/403 , G11C7/04 , G11C7/10 , G11C11/406 , G11C11/4096 , H01L27/10 , G11C7/00
CPC分类号： G11C7/1069 , G11C11/406 , G11C11/40626 , G11C11/4096 , G11C7/1006 , G11C7/1051
摘要： Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式